SLVSEX5A October   2020  – December 2020 TPSM41615

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (PVIN = 12 V)
    7. 6.7 Typical Characteristics (PVIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Setting the Output Voltage
      2. 7.3.2  RS+/RS- Remote Sense Function
      3. 7.3.3  Ramp Select (RAMP and RAMP_SEL)
      4. 7.3.4  Switching Frequency (RT)
      5. 7.3.5  Synchronization (SYNC)
        1. 7.3.5.1 Loss of Synchronization
      6. 7.3.6  Stand-alone/Stackable Operation
        1. 7.3.6.1 Stackable Synchronization
          1. 7.3.6.1.1 Sync Configuration
          2. 7.3.6.1.2 Clock Sync Point Selection
          3. 7.3.6.1.3 Configuration 1: Dual Phase, Primary Sync-Out Clock to Secondary
          4. 7.3.6.1.4 Configuration 2: Dual Phase, Primary and Secondary Sync to External System Clock
      7. 7.3.7  Improved Transient Performance versus Fixed Frequency (Stand-alone Operation Only)
      8. 7.3.8  Output On/Off Enable (EN)
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Soft-Start Operation
      11. 7.3.11 Input Capacitor Selection
      12. 7.3.12 Output Capacitor Selection
      13. 7.3.13 Current Limit (ILIM)
      14. 7.3.14 Safe Start-up into Pre-Biased Outputs
      15. 7.3.15 Overcurrent Protection
      16. 7.3.16 Output Overvoltage and Undervoltage Protection
      17. 7.3.17 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 RAMP Setting
        5. 8.2.2.5 Input Capacitors
        6. 8.2.2.6 Output Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Package Specifications
      2. 10.2.2 EMI
        1. 10.2.2.1 EMI Plots
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.6.1.2 Clock Sync Point Selection

The TPSM41615 device implements a unique clock synchronization scheme for phase interleaving between devices. This is only used when stacking multiple devices. The device will receive a clock signal through the SYNC pin and generate sync points to achieve phase interleaving. Sync point options can be selected with a resistor from the RT pin to AGND. Figure 7-3 shows the clock signals for a primary and a secondary device with a 180° phase shift. See Table 7-7 for clock sync options and the corresponding RT resistor value.

GUID-20201008-CA0I-T9TQ-KBJ8-ZXZN0DBXNZXQ-low.gif Figure 7-3 2-Phase Stackable with 180° Clock Phase Shift
Table 7-7 Sync Point Selection
CLOCK SYNC OPTIONSRT RESISTOR VALUE (kΩ)
0 (0° Interleaving)SHORT
1/2 (180° Interleaving)OPEN