SLVSEW0A September   2020  – December 2020 TPSM41625

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (PVIN = 12 V)
    7. 6.7 Typical Characteristics (PVIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Setting the Output Voltage
      2. 7.3.2  Output Voltage Current Rating
      3. 7.3.3  RS+/RS- Remote Sense Function
      4. 7.3.4  Ramp Select (RAMP and RAMP_SEL)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Synchronization (SYNC)
        1. 7.3.6.1 Loss of Synchronization
      7. 7.3.7  Stand-alone/Stackable Operation
        1. 7.3.7.1 Stackable Synchronization
          1. 7.3.7.1.1 Sync Configuration
          2. 7.3.7.1.2 Clock Sync Point Selection
          3. 7.3.7.1.3 Configuration 1: Dual Phase, Primary Sync-Out Clock to Secondary
          4. 7.3.7.1.4 Configuration 2: Dual Phase, Primary and Secondary Sync to External System Clock
      8. 7.3.8  Improved Transient Performance versus Fixed Frequency (Stand-alone Operation Only)
      9. 7.3.9  Output On/Off Enable (EN)
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Soft-Start Operation
      12. 7.3.12 Input Capacitor Selection
      13. 7.3.13 Output Capacitor Selection
      14. 7.3.14 Current Limit (ILIM)
      15. 7.3.15 Safe Start-up into Pre-Biased Outputs
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Output Overvoltage and Undervoltage Protection
      18. 7.3.18 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 RAMP Setting
        5. 8.2.2.5 Input Capacitors
        6. 8.2.2.6 Output Capacitors
      3. 8.2.3 Application Waveforms
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Package Specifications
      2. 10.2.2 EMI
        1. 10.2.2.1 EMI Plots
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.1 Setting the Output Voltage

The output voltage adjustment range of the TPSM41625 is 0.6 V to 7.1 V. Setting the output voltage requires first setting the internal reference voltage (VREF). The internal reference voltage can be set from 0.6 V to 1.1 V using a resistor (RVSEL) connected from VSEL (pin 28) to AGND (pin 19). Table 7-1 lists reference voltage selections and their corresponding setting resistors. If the required output voltage is the same as the reference voltage, connect the RS+ pin (pin 35) directly to VOUT to set the output voltage as shown in Figure 7-1. Output voltages greater than the reference voltage require an external voltage setting resistor (RADJ) between the RS+ pin and VOUT to set the output voltage as shown in Figure 7-2. The value for RADJ can be calculated using Equation 1 or simply selected from the recommended values given in Table 7-2. Additionally, Table 7-3 includes the recommended switching frequency (FSW), the recommended Ramp resistor (RRAMP), and the minimum output capacitance for several output voltage ranges.

Equation 1. GUID-A54F47CA-B166-4398-9681-7248335FC05A-low.gif

When setting the output voltage, selecting the highest reference voltage will result in the most accurate output voltage set point. The output voltage will be regulated at the connection point of RS+ or RADJ to VOUT. Making the connection near the load improves regulation at the load.

Table 7-1 Setting the Reference Voltage
VREF (V)0.60.70.750.80.850.90.951.01.051.1
RVSEL Value (kΩ)(1)08.6615.423.734.851.178.7open121187
(1) Resistors with ≤ 1% tolerance are recommended.
Table 7-2 Setting the Output Voltage
VOUT (V)0.6 - 1.11.21.51.82.53.35.06.07.0
VREF (V)(1)0.6 - 1.11.11.11.11.11.11.11.11.1
RADJ Value (Ω)(1)short90.936563412702000357044205360
(1) Selecting the highest reference voltage will result in the most accurate output voltage set point.
GUID-B8997675-3CC7-4865-A451-A50E22AE8716-low.gifFigure 7-1 Setting the Output Voltage
(VOUT = VREF)
GUID-96474E5C-EEE6-47D3-8F15-C645C9BFA82F-low.gifFigure 7-2 Setting the Output Voltage
(VOUT > VREF)
Table 7-3 Recommended FSW, RAMP, and Required COUT
PVIN = 5 V
VOUT RANGE (V)RECOMMENDED FSW (kHz)(1)ALLOWABLE FSW RANGE (KHZ)RRAMP (kΩ)MINIMUM REQUIRED COUT (µF)(4)
MINMAXMINIMUM CERAMIC(3)ADDITIONAL REQUIRED CAPACITANCE(5)
0.6< 0.8400300 - < 45078.7294(2)610
500450 - < 550187490
600550 - < 700187300
700700 - 100078.7280
0.8< 1.0400300 - < 45078.7289(2)600
500450 - < 85078.7420
900850 - 100078.7240
1.0< 1.2500400 - 1000187284(2)190
1.2< 1.5500400 - 1000187277(2)100
1.5< 1.8500400 - 1000187266(2)90
1.8< 2.5500400 - 1000187254(2)85
2.53.3500400 - 100078.7224(2)65
PVIN = 12 V
VOUT RANGE (V)RECOMMENDED FSW (kHz)(1)ALLOWABLE FSW RANGE (kHz)RRAMP (kΩ)MINIMUM REQUIRED COUT (µF)(4)
MINMAXMINIMUM CERAMIC(3)ADDITIONAL REQUIRED CAPACITANCE(5)
0.6< 1.0400350 - < 45078.7294(2)760
500450 - < 55078.7430
600550 - 75078.7250
1.0< 1.2400350 - < 50078.7284(2)760
550500 - < 60078.7430
600600 - 100078.7250
1.2< 1.8400350 - < 50078.7277(2)760
500500 - < 600121185
600600 - 1000121100
1.8< 2.5400350 - < 50078.7254(2)600
500500 - < 600187430
600 600 - < 850 187 250
700850 - 100078.790
2.5< 3.3500450 - < 65078.7224(2)450
700650 - < 95018780
1000950 - 100012180
3.3< 5.0600550 - 1000187191(2)65
5.07.1700600 - 1000187134(2)0
(1) The recommended FSW is shown in bold text. Increasing the frequency can reduce the required output capacitance as well as reduce ripple, however it may also reduce efficiency.
(2) This value of minimum ceramic is the effective amount of 6x 47 µF after taking into account DC bias and temperature derating.
(3) The minimum required ceramic output capacitance must account for DC bias and temperature derating.
(4) The Minimum Required output capacitance ensures start-up and stability. Additional output capacitance can be needed to meet transient response requirements.
(5) The Additional Required Capacitance can be either ceramic or low-ESR polymer type. The total required output capacitance must include at least the amount of ceramic type listed in the Minimum Ceramic column.