SLVSEW0A September   2020  – December 2020 TPSM41625

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics (PVIN = 12 V)
    7. 6.7 Typical Characteristics (PVIN = 5 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Setting the Output Voltage
      2. 7.3.2  Output Voltage Current Rating
      3. 7.3.3  RS+/RS- Remote Sense Function
      4. 7.3.4  Ramp Select (RAMP and RAMP_SEL)
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Synchronization (SYNC)
        1. 7.3.6.1 Loss of Synchronization
      7. 7.3.7  Stand-alone/Stackable Operation
        1. 7.3.7.1 Stackable Synchronization
          1. 7.3.7.1.1 Sync Configuration
          2. 7.3.7.1.2 Clock Sync Point Selection
          3. 7.3.7.1.3 Configuration 1: Dual Phase, Primary Sync-Out Clock to Secondary
          4. 7.3.7.1.4 Configuration 2: Dual Phase, Primary and Secondary Sync to External System Clock
      8. 7.3.8  Improved Transient Performance versus Fixed Frequency (Stand-alone Operation Only)
      9. 7.3.9  Output On/Off Enable (EN)
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Soft-Start Operation
      12. 7.3.12 Input Capacitor Selection
      13. 7.3.13 Output Capacitor Selection
      14. 7.3.14 Current Limit (ILIM)
      15. 7.3.15 Safe Start-up into Pre-Biased Outputs
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Output Overvoltage and Undervoltage Protection
      18. 7.3.18 Overtemperature Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Setpoint
        3. 8.2.2.3 Setting the Switching Frequency
        4. 8.2.2.4 RAMP Setting
        5. 8.2.2.5 Input Capacitors
        6. 8.2.2.6 Output Capacitors
      3. 8.2.3 Application Waveforms
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Package Specifications
      2. 10.2.2 EMI
        1. 10.2.2.1 EMI Plots
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Limits apply over TA = –40°C to +105°C, PVIN= 12 V, VIN = 12 V, VOUT = 1.8 V, VREF = 1.0 V, FSW = 500 kHz, IOUT = 25 A, (unless otherwise noted);  Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
PVIN Input switching voltage 4 16 V
VIN Input bias voltage 4 16 V
UVLO PVIN undervoltage lockout PVIN increasing, IOUT = 0 A 3.2 V
PVIN decreasing, IOUT = 2.5 A 3.0 V
VIN undervoltage lockout VIN increasing, IOUT = 0 A 3.8 V
VIN decreasing, IOUT = 2.5 A 3.6 V
IVIN VIN bias current(1) VRS+ = 1.2 V, IOUT = 0 A, EN = OPEN, TA = 25°C 4.3 mA
IVIN-STBY VIN standby current IOUT = 0 A, EN = 0 V, TA = 25°C 4.3 mA
OUTPUT VOLTAGE
VOUT Output voltage adjust RS+ connected directly to VOUT 0.6 1.1 V
RS+ connected to VOUT feedback divider 7.1(1) (2) V
VOUT accuracy 0.6V ≤ VREF ≤ 1.1V, VRS+ = VOUT, IOUT = 0A, -40°C ≤ TJ = TA ≤ 125°C(1) -1.0 1.0 %
Line regulation Over PVIN range, PVIN = VIN, IOUT = 0 A,       TA = 25°C 0.01 %
Load regulation Over IOUT range, TA = 25°C 0.03 %
OUTPUT CURRENT
IOUT Output current Natural convection, TA = 25°C 0 25(2) A
Overcurrent threshold 32 A
ISHARE Current sharing for multi-phase operation(1) IOUT ≤ 20 A/phase ±3 A
IOUT ≥ 20 A/phase ±15%
BP5 REGULATOR
VBP5 BP5 regulator output voltage 4.5 5 5.5 V
VBP5-DROPOUT BP5 regulator dropout voltage(1) VIN = 4.5 V, fSW = 750 kHz, TA = 25°C 365 mV
PERFORMANCE
η Efficiency IOUT = 12.5 A 91 %
RS+
RRS+-RS- Lower feedback resistor                    from RS+ to RS- 0.995 1 1.005 kΩ
ENABLE
VEN-H EN rising threshold IOUT = 0 A 1.45 1.6 1.75 V
VEN-L EN falling threshold IOUT = 2.5 A 1.3 V
IEN_LKG EN input leakage current VIN = 4.5 V, IOUT = 0 A –1 0 1 µA
SOFT START
tSS Soft-start time(1) SS = OPEN 4 ms
tSS-Range Soft-start range(1) Programmable using SS pin 0.5 32 ms
PGOOD
VPGOOD PGOOD thresholds(1) VRS+ rising (fault) 112%
VRS+ falling (good) 105%
VRS+ rising (good) 95%
VRS+ falling (fault) 88%
VPGOOD-LOW PGOOD low voltage with no supply voltage PVIN = VIN = 0 V, IPGOOD = 80 μA 0.8 V
IPGOOD-LKG PGOOD leakage current VIN = 4.5 V, VPGOOD = 5 V, IOUT = 0 A 15 µA
OVP / UVP
VOVP Overvoltage protection threshold(1) VRS+ rising 117%
VUVP Under-voltage protection threshold(1) VRS+ falling 83%
FREQUENCY and SYNC
fSW Switching frequency VSEL = OPEN, RT = 44.2 kΩ, IOUT = 2.5 A 450 500 550 kHz
Switching frequency range(1) IOUT = 2.5 A 300 1000 kHz
ton_min Minimum on-time of SW(1) 30 ns
toff_min Minimum off-time of SW(1) 340 ns
VCLK-H Logic-high for SYNC(1) 2 V
VCLK-L Logic-low for SYNC(1) 0.8 V
TCLK-MIN Minimum pulse width for SYNC(1) SYNC FSW = 500 kHz 100 ns
(1) Ensured by design, not production tested.
(2) To determine IOUT range for a given set of conditions, see the Safe Operating Area graphs in "Typical Characteristics" section of the datasheet for more information.