SLVSFS5A October   2021  – November 2021 TPSM63603

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Characteristics
    7. 6.7  Typical Characteristics
    8. 6.8  Typical Characteristics: VIN = 12 V
    9. 6.9  Typical Characteristics: VIN = 24 V
    10. 6.10 Typical Characteristics: VIN = 36 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Adjustable Output Voltage (FB)
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Output ON/OFF Enable (EN/SYNC) and VIN UVLO
      7. 7.3.7  Frequency Synchronization (EN/SYNC)
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Power Good Monitor (PG)
      10. 7.3.10 Adjustable Switch-Node Slew Rate (RBOOT/CBOOT)
      11. 7.3.11 Internal LDO, VCC Output, and VLDOIN Input
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: 3-A Synchronous Buck Regulator for Industrial Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Connections
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Inverting Buck-Boost Regulator with a –5-V Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 IBB Maximum Output Current
          3. 8.2.2.2.3 Switching Frequency Selection
          4. 8.2.2.2.4 Input Capacitor Selection
          5. 8.2.2.2.5 Output Capacitor Selection
          6. 8.2.2.2.6 Other Connections
        3. 8.2.2.3 Application Curves
        4. 8.2.2.4 EMI
          1. 8.2.2.4.1 EMI Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Package Specifications
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Frequency Synchronization (EN/SYNC)

The TPSM63603 can be synchronized to an external clock using the EN/SYNC pin. The synchronization frequency range is 200 kHz to 2.2 MHz. The internal oscillator can be synchronized by AC coupling a positive clock edge into the EN/SYNC pin, as shown in Figure 7-4. It is recommended to keep the parallel combination value of RENT and RENB in the 100-kΩ range. RENT is required for synchronization, but RENB can be left open. The external clock must be off before start-up to allow proper start-up sequencing. After a valid synchronization signal is applied for 2048 cycles, the clock frequency changes to that of the applied signal.

GUID-3F753C2C-1E7B-46DE-944C-41D1F1989CC3-low.gif Figure 7-4 Typical Synchronization Using the EN/SYNC Pin

Referring to Figure 7-5, the AC-coupled voltage edge at the EN/SYNC pin must exceed the SYNC amplitude threshold, VEN_SYNC, of 2.4 V to trip the internal synchronization pulse detector. In addition, the minimum EN/SYNC rising pulse and falling pulse durations must be longer than the SYNC signal hold time, tSYNC_EDGE, of 100 ns and shorter than the minimum blanking time, tB. A 3.3-V or higher amplitude pulse signal coupled through a 1-nF capacitor, CSYNC, is suggested.

GUID-C5D280BD-9EFE-4830-9241-E0937E71182D-low.gif Figure 7-5 Typical SYNC Waveform