SLVSFS5A October   2021  – November 2021 TPSM63603

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Characteristics
    7. 6.7  Typical Characteristics
    8. 6.8  Typical Characteristics: VIN = 12 V
    9. 6.9  Typical Characteristics: VIN = 24 V
    10. 6.10 Typical Characteristics: VIN = 36 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Adjustable Output Voltage (FB)
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Output ON/OFF Enable (EN/SYNC) and VIN UVLO
      7. 7.3.7  Frequency Synchronization (EN/SYNC)
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Power Good Monitor (PG)
      10. 7.3.10 Adjustable Switch-Node Slew Rate (RBOOT/CBOOT)
      11. 7.3.11 Internal LDO, VCC Output, and VLDOIN Input
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: 3-A Synchronous Buck Regulator for Industrial Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Connections
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Inverting Buck-Boost Regulator with a –5-V Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 IBB Maximum Output Current
          3. 8.2.2.2.3 Switching Frequency Selection
          4. 8.2.2.2.4 Input Capacitor Selection
          5. 8.2.2.2.5 Output Capacitor Selection
          6. 8.2.2.2.6 Other Connections
        3. 8.2.2.3 Application Curves
        4. 8.2.2.4 EMI
          1. 8.2.2.4.1 EMI Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Package Specifications
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 30-Pin QFN,RDH Package(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 RT I Frequency setting pin. This analog pin is used to set the switching frequency between 200 kHz and 2.2 MHz by placing an external resistor from this pin to AGND. Do not leave open or connect to ground.
2 EN/SYNC I Precision enable input pin. High = on, Low = off. Can be connected to VIN. Precision enable allows the pin to be used as an adjustable UVLO. It also functions as the synchronization input pin. Used to synchronize the device switching frequency to a system clock. Triggers on the rising edge of an external clock. A capacitor can be used to AC couple the synchronization signal to this pin. The module can be turned off by using an open-drain or collector device to connect this pin to AGND. An external voltage divider can be placed between this pin, AGND, and VIN to create an external UVLO.
3, 4, 18, 19 VIN P Input supply voltage. Connect the input supply to these pins. Connect input capacitors between these pins and PGND in close proximity to the device. Refer to Section 10.2 for input capacitor placement example.
5, 6, 16, 17, 28, 29 PGND G Power ground. This is the return current path for the power stage of the device. Connect this pad to the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins. See Section 10.2 for a recommended layout.
7-10, 12–15, 30 VOUT P Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND.
11 SW O Switch node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on these pins must be kept to a minimum to prevent issues with noise and EMI.
20 CBOOT I/O Bootstrap pin for internal high-side driver circuitry. A 100-nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. This pin is brought out to use in conjunction with RBOOT to effectively lower the value of the internal RBOOT resistor to adjust the SW node slew rate, if necessary.
21 RBOOT I/O External bootstrap resistor connection. Internal to the device, a 100-Ω bootstrap resistor is connected between this pin and the CBOOT pin. This pin is brought out to use in conjunction with CBOOT to effectively lower the value of the internal RBOOT resistor to adjust the switch node slew rate, if necessary.
22 VLDOIN P Input bias voltage. Supplies the control circuitry of the power module. Input to internal LDO. Connect to an output voltage point to improve efficiency. Connect an optional high quality 0.1-μF to 1-μF capacitor from this pin to ground for improved noise immunity. If the output voltage is above 12 V, connect this pin to ground.
23 VCC O Internal LDO output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high-quality 1-μF ceramic capacitor from this pin to PGND.
24, 27 AGND G Analog ground. Zero voltage reference for internal references and logic. All electrical parameters are measured with respect to this pin. This pin must be connected to PGND at a single point. See Section 10.2 for a recommended layout.
25 FB I Feedback input. For the adjustable output version, connect the mid-point of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. When connecting with feedback resistor divider, keep this FB trace short and as small as possible to avoid noise coupling. See Section 10.2 for a feedback resistor placement. For a fixed output version, connect this pin directly to output capacitor. Do not leave open or connect to ground.
26 PG O Power-good monitor. Open-drain output that asserts low if the feedback voltage is not within the specified window thresholds. A 10-kΩ to 100-kΩ pullup resistor is required to a suitable pullup voltage. If not used, this pin can be left open or connected to PGND.
(1) P = Power, G = Ground, I = Input, O = Output