SLVSFS5A October   2021  – November 2021 TPSM63603

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Characteristics
    7. 6.7  Typical Characteristics
    8. 6.8  Typical Characteristics: VIN = 12 V
    9. 6.9  Typical Characteristics: VIN = 24 V
    10. 6.10 Typical Characteristics: VIN = 36 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Adjustable Output Voltage (FB)
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Switching Frequency (RT)
      6. 7.3.6  Output ON/OFF Enable (EN/SYNC) and VIN UVLO
      7. 7.3.7  Frequency Synchronization (EN/SYNC)
      8. 7.3.8  Spread Spectrum
      9. 7.3.9  Power Good Monitor (PG)
      10. 7.3.10 Adjustable Switch-Node Slew Rate (RBOOT/CBOOT)
      11. 7.3.11 Internal LDO, VCC Output, and VLDOIN Input
      12. 7.3.12 Overcurrent Protection (OCP)
      13. 7.3.13 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1: 3-A Synchronous Buck Regulator for Industrial Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Connections
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2: Inverting Buck-Boost Regulator with a –5-V Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 IBB Maximum Output Current
          3. 8.2.2.2.3 Switching Frequency Selection
          4. 8.2.2.2.4 Input Capacitor Selection
          5. 8.2.2.2.5 Output Capacitor Selection
          6. 8.2.2.2.6 Other Connections
        3. 8.2.2.3 Application Curves
        4. 8.2.2.4 EMI
          1. 8.2.2.4.1 EMI Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Package Specifications
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Power Supply Recommendations

The TPSM63603 buck module is designed to operate over a wide input voltage range of 3 V to 36 V. The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended Operating Conditions in this data sheet. In addition, the input supply must be capable of delivering the required input current to the loaded regulator circuit. Estimate the average input current with Equation 10.

Equation 10. GUID-F9C5BBCE-46EE-4373-B239-1F70BCAF8C63-low.gif

where

  • η = efficiency

If the module is connected to an input supply through long wires or PCB traces with a large impedance, take special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have an adverse affect on module operation. More specifically, the parasitic inductance in combination with the low-ESR ceramic input capacitors form an underdamped resonant circuit, possibly resulting in instability, voltage transients, or both, each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a load transient. If the module is operating close to the minimum input voltage, this dip can cause false UVLO triggering and a system reset.

The best way to solve such issues is to reduce the distance from the input supply to the module and use an electrolytic input capacitor in parallel with the ceramics. The moderate ESR of the electrolytic capacitor helps damp the input resonant circuit and reduce any overshoot or undershoot at the input. A capacitance in the range of 47 μF to 100 μF is usually sufficient to provide input parallel damping and helps hold the input voltage steady during large load transients. A typical ESR of 0.1 Ω to 0.4 Ω provides enough damping for most input circuit configurations.