SLVSGL3 April   2022 TPSM63603E

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  System Characteristics
    7. 7.7  Typical Characteristics
    8. 7.8  Typical Characteristics — VIN = 12 V
    9. 7.9  Typical Characteristics — VIN = 24 V
    10. 7.10 Typical Characteristics — VIN = 36 V
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Output ON and OFF Enable (EN/SYNC) and VIN UVLO
      7. 8.3.7  Frequency Synchronization (EN/SYNC)
      8. 8.3.8  Spread Spectrum
      9. 8.3.9  Power-Good Monitor (PG)
      10. 8.3.10 Adjustable Switch-Node Slew Rate (RBOOT and CBOOT)
      11. 8.3.11 Internal LDO, VCC Output, and VLDOIN Input
      12. 8.3.12 Overcurrent Protection (OCP)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 — 3-A Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
        4. 9.2.1.4 Design 2 — Inverting Buck-Boost Regulator with a –5-V Output
          1. 9.2.1.4.1 Design Requirements
          2. 9.2.1.4.2 Detailed Design Procedure
            1. 9.2.1.4.2.1 Output Voltage Setpoint
            2. 9.2.1.4.2.2 IBB Maximum Output Current
            3. 9.2.1.4.2.3 Switching Frequency Selection
            4. 9.2.1.4.2.4 Input Capacitor Selection
            5. 9.2.1.4.2.5 Output Capacitor Selection
            6. 9.2.1.4.2.6 Other Connections
            7. 9.2.1.4.2.7 EMI
              1. 9.2.1.4.2.7.1 EMI Plots
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
      1. 11.2.1 Package Specifications
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.6 Output ON and OFF Enable (EN/SYNC) and VIN UVLO

The EN/SYNC pin provides precision ON and OFF control for the TPSM63603E. Once the EN/SYNC pin voltage exceeds the threshold voltage and VIN is above the minimum turn-on threshold, the device starts operation. The simplest way to enable the TPSM63603E is to connect EN/SYNC directly to VIN, allowing the TPSM63603E to start up when VIN is within its valid operating range. However, many applications benefit from the employment of an enable divider network as shown in Figure 8-3, which establishes a precision input undervoltage lockout (UVLO). This can be used for sequencing, to prevent re-triggering the device when used with long input cables, or to reduce the occurrence of deep discharge of a battery power source. An external logic signal can also be used to drive the enable input to toggle the output on and off and for system sequencing or protection.

Figure 8-3 VIN UVLO Using the EN/SYNC Pin

RENB can be calculated using Equation 6.

Equation 6.

where

  • RENT is 100 kΩ (typical).
  • VEN is 1.263 V (typical).
  • VIN(ON) is the desired start-up input voltage.
Note: The EN/SYNC pin can also be used as an external synchronization clock input. See Section 8.3.7 for additional information. A blanking time of 4 µs to 28 µs is applied to the enable logic after a clock edge is detected. To effectively disable the output, the EN/SYNC input must stay low for longer than 28 µs. Any logic change within the blanking time is ignored. Blanking time is not applied when the device is in shutdown mode.