SLVSGJ5 April   2022 TPSM63604

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
    8. 7.8 Typical Characteristics (VIN = 12 V)
    9. 7.9 Typical Characteristics (VIN = 24 V)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN/SYNC)
      7. 8.3.7  Frequency Synchronization (EN/SYNC)
      8. 8.3.8  Power Good Monitor (PG)
      9. 8.3.9  Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      10. 8.3.10 Bias Supply Regulator (VCC, VLDOIN)
      11. 8.3.11 Overcurrent Protection (OCP)
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 4-A Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Voltage Setpoint
          2. 9.2.2.2.2 IBB Maximum Output Current
          3. 9.2.2.2.3 Switching Frequency Selection
          4. 9.2.2.2.4 Input Capacitor Selection
          5. 9.2.2.2.5 Output Capacitor Selection
          6. 9.2.2.2.6 Other Considerations
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Design and Layout
    2. 11.2 Layout Example
      1. 11.2.1 Package Specifications
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

Limits apply over TJ = –40°C to 125°C, VIN = 24 V, VOUT = 3.3 V, VLDOIN = 5 V, FSW = 800 kHz (unless otherwise noted). Minimum and maximum limits are specified through production test or by design. Typical values represent the most likely parametric norm and are provided for reference only.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
VIN Input operating voltage range Needed to start up (over the IOUT range) 3.95 36 V
Once operating (over the IOUT range) 3 36 V
VIN_HYS Hysteresis(1) 1 V
IQ_VIN Input operating quiescent current (non-switching)  TA = 25°C, VEN/SYNC = 3.3 V, VFB = 1.5 V 7 µA
ISDN_VIN VIN shutdown quiescent current VEN/SYNC = 0 V, TA = 25°C 1 µA
ENABLE
VEN_RISE EN voltage rising threshold 1.161 1.263 1.365 V
VEN_FALL EN voltage falling threshold 0.91 V
VEN_HYS EN voltage hysteresis  0.303 0.353 0.404 V
VEN_WAKE EN wake-up threshold 0.4 V
IEN Input current into EN/SYNC (non-switching) VEN/SYNC = 3.3 V, VFB = 1.5 V 10 nA
tEN EN high to start of switching delay(1) 0.7 ms
VCC INTERNAL LDO
VCC Internal LDO VCC voltage 3.4 V ≤ VVLDOIN ≤ 12.5 V 3.3 V
VVLDOIN = 3.1 V, non-switching 3.1 V
VCC_UVLO VCC UVLO rising threshold VVLDOIN < 3.1 V(1) 3.6 V
VIN < 3.6 V(2) 3.6 V
VCC_UVLO_HYS VCC UVLO hysteresis(2) Hysteresis below VCC_UVLO 1.1 V
IVLDOIN Input current into VLDOIN pin (non-switching)(3) VEN/SYNC = 3.3 V, VFB = 1.5 V 25 31 µA
FEEDBACK
VOUT Adjustable output voltage range Over the IOUT range 1 16 V
VFB Feedback voltage TA = 25°C, IOUT = 0 A 1.0 V
VFB_ACC Feedback voltage accuracy Over the VIN range, VOUT = 1 V, IOUT = 0 A, FSW = 200 kHz –1% +1%
VFB Load regulation TA = 25°C, 0 A ≤ IOUT ≤ 6 A 0.1%
VFB Line regulation TA = 25°C, IOUT = 0 A, 4 V ≤ VIN ≤ 36 V 0.1%
IFB Input current into FB  VFB = 1 V 10 nA
CURRENT
IOUT Output current TA = 25°C 0 4 A
IOCL Output overcurrent (DC) limit threshold 5.9 A
IL_HS High-side switch current limit Duty cycle approaches 0% 6.0 7.0 8.1 A
IL_LS Low-side switch current limit 4.0 4.8 5.4 A
IL_NEG Negative current limit  –3 A
VHICCUP Ratio of FB voltage to in-regulation FB voltage to enter hiccup Not during soft start 40%
tW Short circuit wait time ("hiccup" time before soft start)(1) 80 ms
SOFT START
tSS Time from first SW pulse to VFB at 90% VIN ≥ 4.2 V 3.5 5 7 ms
tSS2 Time from first SW pulse to release of FPWM lockout if output not in regulation(1) VIN ≥ 4.2 V 9.5 13 17 ms
POWER GOOD
PGOV PG upper threshold – rising % of VOUT setting 105% 107% 110%
PGUV PG lower threshold – falling % of VOUT setting 92% 94% 96.5%
PGHYS PG threshold hysteresis (rising and falling) % of VOUT setting 1.3%
VIN_PG_VALID Input voltage for valid PG output 46-μA pullup, VEN/SYNC = 0 V 1.0 V
VPG_LOW PG low-level output voltage 2-mA pullup to PG pin, VEN/SYNC = 3.3 V 0.4 V
IPG Input current into PG pin when open drain output is high VPG = 3.3 V 10 nA
IOV Pulldown current at the SW node during an overvoltage condition 0.5 mA
tPG_FLT_RISE Delay time to PG high signal 1.5 2.0 2.5 ms
tPG_FLT_FALL Glitch filter time constant for PG function 120 µs
SWITCHING FREQUENCY
fSW_RANGE Switching frequency range by RT or SYNC 200 2200 kHz
fSW_RT1 Default switching frequency by RRT RRT = 66.5 kΩ 180 200 220 kHz
fSW_RT2 Default switching frequency by RRT RRT = 5.76 kΩ 1980 2200 2420 kHz
SYNCHRONIZATION
VEN_SYNC Minimum edge amplitude to sync using EN/SYNC Rise/fall time < 30 ns 2.4 V
tB Blanking of EN after rising or falling edges(1) 4 28 µs
tSYNC_EDGE EN/SYNC signal hold time after edge for edge recognition(1) 100 ns
POWER STAGE
VBOOT_UVLO Voltage on CBOOT pin relative to SW that turns off the high-side switch 2.1 V
tON(min) Minimum ON pulse width(1) VOUT = 1 V, IOUT = 1 A, RBOOT shorted to CBOOT 55 70 ns
tON(max) Maximum ON pulse width(1) 9 µs
tOFF(min) Minimum OFF pulse width VIN = 4 V, IOUT = 1 A, RBOOT shorted to CBOOT 65 85 ns
THERMAL SHUTDOWN
TSHD Thermal shutdown threshold (1) Temperature rising 158 168 180 °C
TSHD-HYS Thermal shutdown hysteresis (1) 10 °C
(1) Parameter specified by design, statistical analysis and production testing of correlated parameters. Not production tested.
(2) Production tested with VIN = 3 V.
(3) This is the current used by the device while not switching, open loop, with FB pulled to +5% of nominal. It does not represent the total
input current to the system while regulating.