SLVSH65A February   2023  – November 2023 TPSM63610E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN)
      7. 8.3.7  Frequency Synchronization (SYNC/MODE)
      8. 8.3.8  Spread Spectrum
      9. 8.3.9  Power-Good Monitor (PG)
      10. 8.3.10 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      11. 8.3.11 Bias Supply Regulator (VCC, VLDOIN)
      12. 8.3.12 Overcurrent Protection (OCP)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Voltage Setpoint
          2. 9.2.2.2.2 IBB Maximum Output Current
          3. 9.2.2.2.3 Switching Frequency Selection
          4. 9.2.2.2.4 Input Capacitor Selection
          5. 9.2.2.2.5 Output Capacitor Selection
          6. 9.2.2.2.6 Other Considerations
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.8 Spread Spectrum

Spread spectrum is configurable using the SPSP pin. Spread spectrum eliminates peak emissions at specific frequencies by spreading these peaks across a wider range of frequencies than a part with fixed-frequency operation. The TPSM63610E implements a modulation pattern designed to reduce low frequency-conducted emissions from the first few harmonics of the switching frequency. The pattern can also help reduce the higher harmonics that are more difficult to filter, which can fall in the FM band. These harmonics often couple to the environment through electric fields around the switch node and inductor. The TPSM63610E uses a ±4% (typical) spread of frequencies which can spread energy smoothly across the FM and TV bands. The device implements Dual Random Spread Spectrum (DRSS). DRSS is a combination of a triangular frequency spreading pattern and pseudorandom frequency hopping. The combination allows the spread spectrum to be very effective at spreading the energy at the following:

  • Fundamental switching harmonic with slow triangular pattern
  • High frequency harmonics with additional psuedorandom jumps at the switching frequency
The advantage of DRSS is its equivalent harmonic attenuation in the upper frequencies with a smaller fundamental frequency deviation. This reduces the amount of input current and output voltage ripple that is introduced at the modulating frequency. Additionally, the TPSM63610E also allows further reduction of the output voltage ripple caused by the spread spectrum modulating pattern. With the SPSP pin grounded, the spread spectrum is disabled. With the SPSP pin tied to VCC, the spread spectrum is on. With the SPSP pin tied through a resistor to ground, the spread spectrum is on. Also, a modulating tone correction is applied to the switcher to reduce the output voltage ripple caused by the frequency modulation. The resistor is usually around 20 kΩ, and can be more precisely calculated using Equation 7. Where IRATED = 8 A for TPSM63610E, L = 2.2µH.

Equation 7. R S P S P k Ω = 14.17 × V I N V O U T V I N - V O U T I R A T E D × L × F S W + 1.22
GUID-20210303-CA0I-53DV-TRGV-QK2WW63VSQHZ-low.pngFigure 8-3 Output Ripple Without Ripple Cancellation Showing VSW (Top), FSW (Middle), VOUT (Bottom)
GUID-20210303-CA0I-0BZP-QWMK-JX2TJ1C2LSND-low.pngFigure 8-4 Output Ripple with Ripple Cancellation Showing VSW (Top), FSW (Middle), VOUT (Bottom)

The spread spectrum is only available while the clock of the TPSM63610E are free running at their natural frequency. Any of the following conditions overrides spread spectrum, turning it off:

  • The clock is slowed due to operation at low input voltage. This is operation in dropout.
  • The clock is slowed under light load in auto mode. This is normally not seen above 750-mA load. Note that if the device is operating in FPWM mode, spread spectrum is active, even if there is no load.
  • The clock is slowed due to high input-to-output voltage ratio. This mode of operation is expected if on-time reaches minimum on time.