SLVSH65A February   2023  – November 2023 TPSM63610E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN)
      7. 8.3.7  Frequency Synchronization (SYNC/MODE)
      8. 8.3.8  Spread Spectrum
      9. 8.3.9  Power-Good Monitor (PG)
      10. 8.3.10 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      11. 8.3.11 Bias Supply Regulator (VCC, VLDOIN)
      12. 8.3.12 Overcurrent Protection (OCP)
      13. 8.3.13 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  10. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Design 2 – Inverting Buck-Boost Regulator with Negative Output Voltage
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Output Voltage Setpoint
          2. 9.2.2.2.2 IBB Maximum Output Current
          3. 9.2.2.2.3 Switching Frequency Selection
          4. 9.2.2.2.4 Input Capacitor Selection
          5. 9.2.2.2.5 Output Capacitor Selection
          6. 9.2.2.2.6 Other Considerations
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.11 Bias Supply Regulator (VCC, VLDOIN)

VCC is the output of the internal LDO subregulator used to supply the control circuits of the TPSM63610E. The nominal VCC voltage is 3.3 V. The VLDOIN pin is the input to the internal LDO. Connect this input to VOUT to provide the lowest possible input supply current. If the VLDOIN voltage is less than 3.1 V, VIN1 and VIN2 directly power the internal LDO.

To prevent unsafe operation, VCC has UVLO protection that prevents switching if the internal voltage is too low. See VCC_UVLO and VCC_UVLO_HYS in the Electrical Characteristics.

VCC must not be used to power external circuitry. Do not load VCC or short it to ground. VLDOIN is an optional input to the internal LDO. Connect an optional high quality 0.1-µF to 1-µF capacitor from VLDOIN to AGND for improved noise immunity.

The LDO provides the VCC voltage from one of two inputs: VIN or VLDOIN. When VLDOIN is tied to ground or below 3.1 V, the LDO derives power from VIN. The LDO input becomes VLDOIN when VLDOIN is tied to a voltage above 3.1 V. The VLDOIN voltage must not exceed both VIN and 12 V.

Equation 8 specifies the LDO power loss reduction as:

Equation 8. PLDO-LOSS = ILDO × (VIN-LDO – VVCC)

The VLDOIN input provides an option to supply the LDO with a lower voltage than VIN, thus minimizing the LDO input voltage relative to VCC and reducing power loss. For example, if the LDO current is 10 mA at 1 MHz with VIN = 24 V and VOUT = 5 V, the LDO power loss with VLDOIN tied to ground is 10 mA × (24 V – 3.3 V) = 207 mW, while the loss with VLDOIN tied to VOUT is equal to 10 mA × (5 V – 3.3 V) = 17 mW – a reduction of 190 mW.

Figure 9-22 and Figure 8-7 show typical efficiency plots with and without VLDOIN connected to VOUT.

GUID-20220819-SS0I-RQTS-WZ7J-FZLRN48J1MS8-low.svg
VIN = 24 V VOUT = 5 V FSW = 1 MHz
Figure 8-6 Efficiency Increase with External Bias
GUID-20220819-SS0I-4NR2-TKWM-HGFS7SMKJJ6G-low.svg
VIN = 36 V VOUT = 5 V FSW = 1 MHz
Figure 8-7 Efficiency Increase with External Bias