SLVSHL0D June   2024  – December 2024 TPSM81033

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 System Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Lockout
      2. 6.3.2  Enable and Soft Start
      3. 6.3.3  Setting the Output Voltage
      4. 6.3.4  Current Limit Operation
      5. 6.3.5  Pass-Through Operation
      6. 6.3.6  Power Good Indicator
      7. 6.3.7  Implement Output Discharge by PG function
      8. 6.3.8  Overvoltage Protection
      9. 6.3.9  Output Short-to-Ground Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power-Save Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting the Output Voltage
        2. 7.2.2.2 Output Capacitor Selection
        3. 7.2.2.3 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPSM81033 8-Pin QFN-FCMOD, VCD PackageTop View Figure 4-1 8-Pin QFN-FCMOD, VCD PackageTop View
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
PVIN 1 PWR Power supply input.
GND 2 PWR Ground pin of the IC.
EN 3 I Enable logic input. Logic high voltage enables the device. Logic low voltage disables the device and turns it into shutdown mode.
MODE 4 I Operation mode selection in the light load condition. When it is connected to logic high voltage, the device works in forced PWM mode. When it is connected to logic low voltage, the device works in auto PFM mode.
PG 5 O Power good indicator and open drain output.
FB 6 I Voltage feedback of adjustable output voltage, when FB connect to AVIN, output voltage is fixed 5.0V
VOUT 7 PWR Boost converter output.
AVIN 8 I IC power supply input. TI recommends to connect it with PVIN pin.
SW – – Switch pin of the power stage. This pin can be left floating