SLVSHL0C June   2024  – September 2024 TPSM81033

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Undervoltage Lockout
      2. 6.3.2 Enable and Soft Start
      3. 6.3.3 Setting the Output Voltage
      4. 6.3.4 Pass-Through Operation
      5. 6.3.5 Power Good Indicator
      6. 6.3.6 Implement Output Discharge by PG function
      7. 6.3.7 Overvoltage Protection
      8. 6.3.8 Output Short-to-Ground Protection
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power-Save Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting the Output Voltage
        2. 7.2.2.2 Output Capacitor Selection
        3. 7.2.2.3 Input Capacitor Selection
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
  • VCD|9
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6 Implement Output Discharge by PG function

The purpose of the output discharge function is to ensure a defined down-ramp of the output voltage and to let the output voltage close to 0V quickly when the device is being disabled. TPSM81033 can implement output discharge function by PG function that requires a RDummy resistor connected between PG pin and Vout pin. PG is an open drain NMOS architecture with up to 50mA current capability, the PG pin becomes logic high when the output voltage reaches the target value, so the dummy load resistor does not lead any power loss during normal operation. When the EN pin gets low, the TPSM81033 is disabled and meanwhile the PG pin gets low with a typical 33μs glitch time (tglitch). With PG pin keeps low, the RDummy works as a dummy load to discharge output voltage. Changing RDummy can adjust the output discharge rate.

TPSM81033 Implement Output Discharge by PG function Figure 6-1 Implement Output Discharge by PG function