SLVSHL0D June   2024  – December 2024 TPSM81033

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 System Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Lockout
      2. 6.3.2  Enable and Soft Start
      3. 6.3.3  Setting the Output Voltage
      4. 6.3.4  Current Limit Operation
      5. 6.3.5  Pass-Through Operation
      6. 6.3.6  Power Good Indicator
      7. 6.3.7  Implement Output Discharge by PG function
      8. 6.3.8  Overvoltage Protection
      9. 6.3.9  Output Short-to-Ground Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power-Save Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting the Output Voltage
        2. 7.2.2.2 Output Capacitor Selection
        3. 7.2.2.3 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6 Power Good Indicator

The TPSM81033 integrates a power good indicator to simplify sequencing and supervision. The power-good output consists of an open-drain NMOS, requiring an external pullup resistor connect to a suitable voltage supply. The PG pin goes high with a typical 1.3ms delay time after VOUT is between 93% (typical) and 107% (typical) of the target output voltage, the hysterisys windown is about 2.5% (typical). When the output voltage is out of the target output voltage window, the PG pin immediately goes low with a 33μs deglitch filter delay. This deglitch filter also prevents any false pulldown of the PGOOD due to transients. When EN is pulled low, the PG pin is also forced low with a 33μs deglitch filter delay. If not used, the PG pin can be left floating or connected to GND.