SLVSHL0D June   2024  – December 2024 TPSM81033

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 System Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Undervoltage Lockout
      2. 6.3.2  Enable and Soft Start
      3. 6.3.3  Setting the Output Voltage
      4. 6.3.4  Current Limit Operation
      5. 6.3.5  Pass-Through Operation
      6. 6.3.6  Power Good Indicator
      7. 6.3.7  Implement Output Discharge by PG function
      8. 6.3.8  Overvoltage Protection
      9. 6.3.9  Output Short-to-Ground Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Power-Save Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting the Output Voltage
        2. 7.2.2.2 Output Capacitor Selection
        3. 7.2.2.3 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to 125°C, VIN = 3.6 V and VOUT = 5.0 V. Typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIN Input voltage range 1.8 5.5 V
VIN_UVLO Under-voltage lockout threshold VIN rising 1.7 1.79 V
VIN falling 1.6 V
VIN_HYS VIN UVLO hysteresis 65 mV
IQ Quiescent current into AVIN pin IC enabled, No load, No switching VAVIN = 1.8 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C 13 20 25 µA
Quiescent current into VOUT pin IC enabled, No load, No switching VOUT = 2.2 V to 5.5 V, VFB = VREF + 0.1 V, TJ up to 125°C 5.3 8.4 µA
ISD Shutdown current into AVIN and PVIN pin IC disabled, VAVIN = VPVIN = 3.6 V, TJ = 25°C 0.1 0.2 µA
OUTPUT
VOUT Output voltage setting range 2.2 5.5 V
VOUT (fixed 5V) Fixed output voltage FB connected to AVIN
VIN < VOUT, PWM mode		 4.93 5 5.07 V
VREF Reference voltage at the FB pin PWM mode 591 600 609 mV
VREF Reference voltage at the FB pin PFM mode 606 mV
VOVP Output over-voltage protection threshold VOUT rising 5.5 5.75 6.0 V
VOVP_HYS Over-voltage protection hysteresis 0.11 V
IFB_LKG Leakage current at FB pin TJ = 25°C 4 25 nA
IFB_LKG Leakage current at FB pin TJ = 125°C 5 30 nA
IVOUT_LKG Leakage current into VOUT pin IC disabled, VAVIN = 0 V, VPVIN = 0 V, VOUT = 5.5 V, TJ = 25°C 0.2 0.5 µA
POWER SWITCH
RDS(on) High-side MOSFET on resistance VOUT = 5.0 V 46 mΩ
RDS(on) Low-side MOSFET on resistance VOUT = 5.0 V 22 mΩ
fSW Switching frequency VAIN = 3.6 V, VOUT = 5.0 V, PWM mode 2.0 2.4 2.8 MHz
ILIM_SW Valley current limit VAVIN = 3.6 V, VOUT = 5.0 V, MODE=0 1.45 2 2.25 A
ILIM_SW Valley current limit VAVIN = 3.6 V, VOUT = 5.0 V, MODE=1 1.4 1.95 2.2 A
IREVERSE Reverse current limit (MODE=1) VAVIN = 3.6 V, VOUT = 5.0 V; MODE = 1 -1.4 A
ILIM_CHG Pre-charge current(1) VAVIN = 1.8 - 5.5 V, VOUT < 0.4 V 330 mA
LOGIC INTERFACE
VEN_H EN logic high threshold VAVIN > 1.8 V or VOUT > 2.2 V 1.2 V
VEN_L EN logic low threshold VAVIN > 1.8 V or VOUT > 2.2 V 0.4 V
VMODE_H MODE Logic high threshold VAVIN > 1.8 V or VOUT > 2.2 V 1.2 V
VMODE_L MODE Logic Low threshold VAVIN > 1.8 V or VOUT > 2.2 V 0.4 V
RDOWN EN pins internal pull-down resistor 10 MΩ
RDOWN MODE pins internal pull-down resistor 1 MΩ
PROTECTION
TSD Thermal shutdown threshold(1) TJ rising 170 °C
TSD Thermal shutdown threshold(1) TJ falling 155 °C
TSD_HYS Thermal shutdown hysteresis(1) TJ falling below TSD 15 °C
(1) Specified by characterization. Not production tested.