SLVSHG7A September   2024  – November 2024 TPSM82843

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Enable and Shutdown (EN)
      2. 7.3.2 Soft Start
      3. 7.3.3 VSET Pin: Output Voltage Selection
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Switch Current Limit, Short-Circuit Protection
      6. 7.3.6 Thermal Shutdown
      7. 7.3.7 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Save Mode Operation
      2. 7.4.2 100% Mode Operation
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • VCF|7
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

The pinout of TPSM82843 has been designed to enable a single top layer PCB routing of the IC and the critical passive components such as CIN, COUT, and VSET resistor. Furthermore, this pinout allows the user to connect tiny components such as 0201 (0603 metric) size capacitors and resistors. As for all switching power supplies, the layout is an important step in the design. Care must be taken in board layout to get the specified performance. Providing a low inductance, low impedance ground path is critical. Therefore, use wide and short traces for the main current paths. Place the input capacitor as close as possible to the VIN of the IC and GND pins. This placement is the most critical component placement. Then place the output capacitor without via as close as possible to the VOUT and GND pin as shown in the following layout diagram. The VOS line is a sensitive, high impedance input and must be connected to the output capacitor with a direct trace from the output capacitor solder pad to the device pin. The VOS line must stay away from noisy components and traces (for example, the SW line) or other noise sources. For bode measurements in the evaluation board, a via is placed on the trace to allow connection of a 10Ohm resistor between the capacitor pad and VOS on the bottom side of the PCB. The connection between capacitor pad and via must be cut for this measurement. For the final circuit, no vias can be present and all capacitors must be placed on the top layer.