SLVSGS7D July   2023  – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced-PWM and Power-Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Setpoint
        2. 7.3.6.2 Output Voltage Range
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling (DVS)
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection / Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current-Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.14.2 Power-Good Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Four TPSM8287Axx in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –40 °C to 125 °C, and VIN = 2.7 V to 6 V. Typical values at VIN = 3.3 V and TJ = 25 °C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ_VIN Quiescent current (VIN) EN = high, IOUT = 0 mA, V(SW) = 0 V, SINGLE=1, MODE/SYNC = low, device not switching, TJ = 25 °C 1.5 3 mA
ISD Shutdown current (VIN) EN = low, V(SW) = 0 V, TJ = 25 °C 16.5 40 µA
VIT+(UVLO) Positive-going UVLO threshold voltage (VIN) 2.5 2.6 2.7 V
VIT–(UVLO) Negative-going UVLO threshold voltage (VIN) 2.4 2.5 2.6 V
Vhys(UVLO) UVLO hysteresis voltage (VIN) 90 mV
VIT+(OVLO) Positive-going OVLO threshold voltage (VIN) 6.1 6.3 6.5 V
VIT–(OVLO) Negative-going OVLO threshold voltage (VIN) 6.0 6.2 6.4 V
Vhys(OVLO) OVLO hysteresis voltage (VIN) 85 mV
VPOR– Negative-going power-on reset (POR) threshold (VIN) 1.4 V
TSD Thermal shutdown threshold temperature TJ rising 170 °C
Thermal shutdown hysteresis 20 °C
TW Thermal warning threshold temperature TJ rising 150 °C
Thermal warning hysteresis 20 °C
CONTROL and INTERFACE
VIT+ Positive-going input threshold voltage (EN) 0.97 1.0 1.03 V
VIT– Negative-going input threshold voltage (EN) 0.87 0.9 0.93 V
Vhys Hysteresis voltage (EN) 95 mV
IIH High-level input current (EN) VEN = VIN, internal pulldown resistor disabled 200 nA
IIL Low-level input current (EN) VEN = 0 V, internal pulldown resistor disabled –200 nA
VIH High-level input voltage (SDA, SCL, MODE/SYNC) 0.8 V
VIL Low-level input voltage (SDA, SCL, MODE/SYNC) 0.4 V
VOL Low-level output voltage (SDA) IOL = 9 mA 0.4 V
IOL = 5 mA 0.2 V
ILKG Input leakage current into SDA, SCL VOH = 3.3 V 200 nA
IIL Low-level input current (MODE/SYNC) VMODE/SYNC = 0 V –150 150 nA
IIH High-level input current (MODE/SYNC) VMODE/SYNC = VIN 3 µA
td(EN)1 Enable delay time when EN tied to VIN Measured from when EN goes high to when device starts switching
SRVIN = 1 V/µs		 210 535 µs
td(EN)2 Enable delay time when VIN already applied Measured from when EN goes high to when device starts switching 40 100 µs
td(RAMP) Output voltage ramp time Measured from when device starts switching to rising edge of PG. Selectable with I2C.  See Table 8-5.  0.46 0.54 0.62 ms
0.88 1.04 1.20 ms
1.73 2.04 2.35 ms
3.43 4.04 4.65 ms
TSYNC_LOCK Time to lock external frequency 50 µs
f(SYNC) Synchronization clock frequency range (MODE/SYNC) TPSM8287A06BAS, TPSM8287A10BAH,
TPSM8287A12BAS, TPSM8287A15BAH		 1.3 2.0 MHz
f(SYNC) Synchronization clock frequency range (MODE/SYNC) TPSM8287A12BBS, TPSM8287A15BBH 1.8 2.7 MHz
D(SYNC) Synchronization clock duty cycle range (MODE/SYNC) 45 55
VT+(UVP) Positive-going power good threshold voltage (output undervoltage) 94 96 98 %VOUT
VT–(UVP) Negative-going power good threshold voltage (output undervoltage) 92 94 96 %VOUT
VT+(OVP) Positive-going power good threshold voltage (output overvoltage) 104 106 108 %VOUT
VT–(OVP) Negative-going power good threshold voltage (output overvoltage) 102 104 106 %VOUT
VOL Low-level output voltage (PG) IOL = 10 mA 0.3 V
ILKG Input leakage current into PG VOH = 3.3 V 200 nA
VIH High-level input voltage (PG) Device configured as a secondary device in stacked operation 0.8 V
VIL Low-level input voltage (PG) Device configured as a secondary device in stacked operation 0.4 V
IIH High-level input current (PG) Device configured as a secondary device in stacked operation 1 µA
IIL Low-level input current (PG) Device configured as a secondary device in stacked operation –1 µA
td(PG) Deglitch time (PG) High-to-low or low-to-high transition on the PG pin 34 40 46 µs
OUTPUT
VOUT Output voltage accuracy VIN ≥ VOUT + 1.4 V –0.8 0.8 %
VICR Input common-mode range (VOSNS) –100 VO(nom) + 100 mV
VICR Input common-mode range (GOSNS) –100 100 mV
fSW Switching frequency (SW) fSW = 1.5 MHz, PWM operation, VIN = 3.3 V, VOUT = 0.75 V 1.35 1.5 1.65 MHz
fSW = 2.25 MHz, PWM operation, VIN = 3.3 V, VOUT = 0.75 V 2.025 2.25 2.475
fmod Frequency of the spread-spectrum sweep fsw/2048 kHz
ΔfSW Switching frequency variation during spread-spectrum operation ±10%
τ Emulated current time constant 12.5 µs
gm Error amplifier transconductance 1.5 mS
ILIM High-side FET forward switch current limit, DC TPSM8287A06BAS 8 11 13 A
TPSM8287A10BAH 14.5 17.5 19.5
TPSM8287A12BAS, TPSM8287A12BBS 15 19 21
TPSM8287A15BAH, TPSM8287A15BBH 18 23 25
Low-side FET negative current limit, DC 7.5 12 A