SLVSGS7D July   2023  – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced-PWM and Power-Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Setpoint
        2. 7.3.6.2 Output Voltage Range
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling (DVS)
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection / Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current-Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.14.2 Power-Good Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Four TPSM8287Axx in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions


TPSM8287A06 TPSM8287A10 TPSM8287A12 TPSM8287A15 TPSM8287Axx RDV and RDW Package, B0QFN 39 Pin
Figure 5-1 TPSM8287Axx RDV and RDW Package, B0QFN 39 Pin
Table 5-1 Pin Functions
PINTYPE(1)DESCRIPTION
NO.NAME
35GOSNSIOutput ground sense (differential output voltage sensing). Connect at the load.
36VOSNSIOutput voltage sense (differential output voltage sensing). Connect at the load.
1ENIThis pin is the enable pin of the device. The user must connect to it using a series resistor of at least 15 kΩ. A low logic level on this pin disables the device, and a high logic level on this pin enables the device. Do not leave this pin unconnected.

For stacked operation, connect the EN pins of all stacked devices together with a resistor to the supply voltage or a GPIO of a processor. See Stacked Operation for a detailed description.

4, 27VINPPower supply input. Connect an input capacitor as close as possible between each VIN and GND (on both sides of the package).
5, 6, 7, 8, 24, 25, 26GNDGNDGround pin
9 - 22VOUTPOutput voltage pin
23SWOThis pin is the switch pin of the converter and is connected to the internal Power MOSFETs. This pin can be left floating.
33PGI/O

Open-drain power-good output with window comparator. This pin is pulled to GND while VOUT is outside the power-good threshold. This pin can be left open or tied to GND if not used in single device operation. A pullup resistor can be connected to any voltage not larger than 6.5 V.

In stacked operation, connect the PG pins of all stacked devices together. Only the PG pin of the primary converter in stacked operation is an open drain output. For devices that are defined as secondary converters in stacked mode, the pin is an input pin. See Stacked Operation for a detailed description.

29MODE/SYNCI

The device runs in power save mode when this pin is pulled low. If the pin is pulled high, the device runs in forced-PWM mode. If unused, this pin can be left floating and an internal pulldown resistor pulls it low. The pin can also be used to synchronize the device to an external clock. See Section 7.3.8 for a detailed description.

30SDAI/OI2C serial data pin. Do not leave floating. Connect a pullup resistor to a logic high level.

For secondary devices in stacked operation, or if the I2C interface is not used, connect the pin to GND.

31SCLII2C serial clock pin. Do not leave this pin floating. Connect a pullup resistor to a logic high level.

For secondary devices in stacked operation, or if the I2C interface is not used, connect the pin to GND.

32SYNC_OUTI/OInternal clock output pin for synchronization in stacked mode. Leave this pin floating for single device operation. Connect this pin to the MODE/SYNC pin of the next device in the daisy-chain in stacked operation. Do not use this pin to connect to a non-TPSM8287Axx device.

During start-up, this pin is used to identify if a device must operate as a secondary converter in stacked operation. Connect a 47-kΩ resistor from this pin to GND to define a secondary converter in stacked operation. See Stacked Operation for a detailed description.

28VSET1I/OStart-up output voltage and I2C address selection pin. A resistor or short circuit to GND or VIN defines the selected output voltage and I2C address. See Table 7-2.
3VSET2I/O
2VSET3I/O
34COMPI/ODevice compensation input. A resistor and capacitor from this pin to GOSNS define the compensation of the control loop.

In stacked operation, connect the COMP pins of all stacked devices together and connect a resistor and capacitor between the common COMP node and GOSNS.

37, 38GND Exposed Thermal Pad—

The thermal pad must be soldered to GND to achieve an appropriate thermal resistance and for mechanical stability.

39

VOUT

Exposed Thermal Pad		—The thermal pad must be soldered to VOUT to achieve an appropriate thermal resistance and for mechanical stability.
(1) I = input, O = output, P = power, GND = ground