SLVSGS7 Data sheet

SLVSGS7D July 2023 – June 2024 TPSM8287A06 , TPSM8287A10 , TPSM8287A12 , TPSM8287A15

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RDW|39
- MPQF792A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

9.2.2.4 Selecting the Output Capacitors

In practice, the total output capacitance is typically comprised of a combination of different capacitors, in which larger capacitors provide the load current at lower frequencies and smaller capacitors provide the load current at higher frequencies to satisfy the load impedance requirements. The value, type, and location of the output capacitors are typically defined by the load. TI recommends X7R multilayer ceramic capacitors (MLCCs) for best filtering and must be placed between both VOUT and GND pins, as close as possible to those pins. For applications with ambient temperatures below 85°C, capacitors with an X5R dielectric can be used. Ceramic capacitors have a DC-Bias effect, which has a strong influence on the final effective capacitance. Choose the right capacitors carefully in combination with considering the package size and voltage rating. The below calculations use the effective value of the total output capacitance.

The TPSM8287Axx devices feature a butterfly or parallel layout with VOUT and GND pins on opposite sides of the package. This feature allows the output capacitors to be placed symmetrically on the PCB such that the electromagnetic fields cancel each other out, thereby reducing EMI.

The TPSM8287Axx device is optimized to support harsh load transients. The device external loop compensation tunes the loop response to the desired response with a given output capacitance. The below calculations create designs that meet the load step specified in Table 9-4. These calculations typically result in total output capacitances of several hundred µF.

Best output voltage regulation is achieved when the TPSM8287Axx device, the output capacitors, and load are placed very close to each other, keeping the distance and added inductance between the device and load to the absolute minimum.

In case this placement can not be achieved, then the majority of the total capacitance must be located at the load, with just two capacitors located at the TPSM8287Axx device. TI recommends that the capacitance located at the load be at least twice the amount of the capacitance located at the device.

If the application does not contain harsh load transients, then smaller values of output capacitances are possible. Do not use output capacitances below the minimum values in Recommended Operating Conditions.

The transient response of the converter is defined by one of two criteria:

The slew rate of the current through the inductor, in which case the feedback loop of the converter saturates.
The loop bandwidth, in which the converter stays in regulation, and the loop does not saturate (BW_τ < f_SW / 4)

Which of the above criteria applies in any given application depends on the operating conditions and component values used. Calculate the output capacitance for both cases and select the higher of the two values.

If the converter remains in regulation, the minimum required output capacitance is given by:

Equation 17.

C_{O U T (m i n) (r e g)} = (\frac{τ \times (1 + g_{m} \times R_{Comp1})}{2 \times π \times \frac{L}{Nɸ} \times {BW}_{τ}}) (1 + \sqrt{{T O L}_{τ}^{2} + {T O L}_{I N D}^{2} + {T O L}_{f S W}^{2}})

Equation 18.

C_{O U T (m i n) (r e g)} = (\frac{12.5 \times 10^{- 6} \times (1 + 1.5 \times 10^{- 3} \times 806)}{2 \times π \times \frac{100 \times 10^{- 9}}{1} \times 300 \times 10^{3}}) (1 + \sqrt{{30 %}^{2} + {20 %}^{2} + {10 %}^{2}}) = 201.3 μ F

If the converter loop saturates, the minimum output capacitance is given by:

Equation 19.

C_{O U T (m i n) (s a t)} = \frac{1}{∆ V_{O U T}} (\frac{L \times {∆ I_{OUT(max)}}^{2}}{2 \times V_{O U T} \times Nɸ} - \frac{∆ I_{OUT(step)} \times t_{t}}{2}) (1 + {T O L}_{I N D})

Equation 20.

C_{O U T (m i n) (s a t)} = \frac{1}{27 \times 10^{- 3}} (\frac{100 \times 10^{- 9} \times {9.7}^{2}}{2 \times 0.9 \times 1} - \frac{8.0 \times 1 \times 10^{- 6}}{2}) (1 + 20 %) = 54.5 μ F

In this case, choose C_OUT(min) = 201.3 µF as the larger of the two values for the output capacitance.

Table 9-3 lists the three output capacitors chosen. 2 × 47-µF capacitors are placed close to the IC, giving a minimum effective capacitance of about 27 µF each. A single 220-µF capacitor is placed near the load to approximate the total decoupling capacitance required by a typical load. This 220-µF capacitor yields about 138 µF of effective capacitance. Together, the 192 µF of effective capacitance is very close to the required minimum value calculated above. For further calculations, use C_OUT = 192 µF.

Equation 50 checks that most of the output capacitance is placed at the load. If the ratio is less than 1, increase the capacitance at the load or place the device, output capacitance, and load next to each other such that there is no separation between the output capacitances.

Equation 21.

\frac{C_{LOAD}}{2 {\times C}_{OUT}} > 1

Equation 22.

\frac{138 \times 10^{- 6}}{2 \times (2 \times 27 \times 10^{- 6})} > 1

= True

Equation 23 calculates the output voltage ripple, based on the effective output capacitance value.

Equation 52.

V_{O U T (p - p)} = \frac{I_{L (PP)}}{8 \times C_{OUT} \times f_{s w}}

Equation 53.

V_{O U T (p - p)} = \frac{3.4}{8 \times 192 \times 10^{- 6} \times 2.25 \times 10^{6}} = 0.984 m V

The ripple is slightly higher in the application, due to the ESR and ESL in the output capacitors and the application board parasitics.