SLVSHR7 August 2024 TPSM8287A12M , TPSM8287A15M
PRODUCTION DATA
The TPSM8287A1xM devices feature a butterfly or parallel layout with two pairs of VIN and GND pins on opposite sides of the package.
The duty cycle of the converter is given by:
The value of input capacitance needed to meet any system-level input voltage ripple requirement is given by Equation 42. For this example, the lowest input voltage and highest load current are used to generate a worst case input voltage ripple of 100mV.
The value of CIN calculated with Equation 42 is the effective capacitance after all derating, tolerance, and aging effects have been considered. In this parallel configuration, make sure to distribute the calculated input capacitance equally across all phases.