SLVSG64B February   2022  – November 2022 TPSM82903

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Mode Selection and Device Configuration (MODE/S-CONF)
      2. 7.3.2 Adjustable VO Operation (External Voltage Divider)
      3. 7.3.3 Setable VO Operation (VSET and Internal Voltage Divider)
      4. 7.3.4 Soft Start/Tracking (SS/TR)
      5. 7.3.5 Smart Enable with Precise Threshold
      6. 7.3.6 Power Good (PG)
      7. 7.3.7 Undervoltage Lockout (UVLO)
      8. 7.3.8 Current Limit And Short Circuit Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Pulse Width Modulation (PWM) Operation
      2. 7.4.2 AEE (Automatic Efficiency Enhancement)
      3. 7.4.3 Power Save Mode Operation (Auto PFM/PWM)
      4. 7.4.4 100% Duty-Cycle Operation
      5. 7.4.5 Output Discharge Function
      6. 7.4.6 Starting into a Pre-Biased Load
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application with Adjustable Output Voltage
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Programming the Output Voltage
        3. 8.2.2.3 Capacitor Selection
          1. 8.2.2.3.1 Output Capacitor
          2. 8.2.2.3.2 Input Capacitor
          3. 8.2.2.3.3 Soft-Start Capacitor
        4. 8.2.2.4 Tracking Function
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application with Setable VO Using VSET
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
        1. 8.5.2.1 Thermal Considerations
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

VI = 3 V to 17 V, TJ = -40°C to +125°C, Typical values at VI = 12.0 V and TA = 25°C,unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ_PSM Operating Quiescent Current (Power Save Mode) Iout = 0 mA, device not switching 4 µA
IQ_PWM Operating Quiescent Current (PWM Mode) VIN=12 V, VOUT=1.2 V; Iout = 0 mA,  device switching 8 mA
ISD Shutdown current into VIN pin EN = 0 V 0.27 3.5 µA
VUVLO Under Voltage Lock-Out VIN rising 2.85 2.925 3.0 V
Under Voltage Lock-Out VIN falling 2.7 2.775 2.85 V
VUVLO_HYS Under Voltage Lock-Out Hysteresis Hysteresis 150 mV
CONTROL & INTERFACE
ILKG EN Input leakage current EN = 12 V 10 300 nA
VIH_MODE High-Level Input Voltage at MODE/S-CONF-Pin 1.0 V
TSD Thermal Shutdown Threshold TJ rising 170 °C
Thermal Shutdown Hysteresis Hysteresis 20
VIH High-level input voltage at EN-Pin 0.97 1.0 1.03 V
VIL Low-level input voltage at EN-Pin 0.87 0.9 0.93 V
REN_PD Smart-Enable Internal Pulldown Resistor EN = LOW 0.5 MΩ
VPG Power good threshold VFB rising, referenced to VFB nominal 93.5% 96% 99%
VFB falling, referenced to VFB nominal 88.5% 93% 96%
Hysteresis 1.5% 3.5% 6%
VPG_OL Low-level output voltage at PG pin ISINK = 1 mA 0.4 V
IPG_LKG Input leakage current into PG pin VPG = 5 V 15 550 nA
tPG_DLY Power good delay time VFB falling 32 µs
RSET S-CONF/VSET Resistor Tolerance –4 +4 %
CSET Maximum Capacitance connected to S-CONF/VSET Pins 30 pF
POWER SWITCHES
ILKG_SW Leakage current into SW-Pin VSW = VOS = 5.5 V 2 7 µA
RDS_ON High-side FET on resistance VIN > 4 V, ISW = 500 mA 62 111 mΩ
Low-side FET on resistance VIN > 4 V, ISW = 500 mA 22 40
ILIM High-side FET current limit 4.1 4.9 5.8 A
Low-side FET current limit 3.8 4.3 4.7 A
ILIM_SINK Low-side FET sink current limit 1.3 1.7 2.5 A
fSW Switching frequency 2.5-MHz selection 2.5 MHz
TON(MIN) Minimum On-time 50 ns
fSW Switching frequency 1.0-MHz selection 1.0 MHz
D Dutycycle 1
RPD Dropout resistance 100% mode, VIN > 4 V 100 mΩ
OUTPUT
VO_Reg1 Output Voltage Regulation VSET Configuration selected. TJ = 25°C. –0.9% +0.9%
VO_Reg2 Output Voltage Regulation VSET Configuration selected. 0 °C< TJ < 85°C –1.1% +1.1%
VO_Reg3 Output Voltage Regulation VSET Configuration selected. –40°C < TJ < 125°C –1.25% +1.25%
VFB Feedback Regulation Voltage Adjustable Configuration selected 0.6 V
VFB_Reg1 Feedback Voltage Regulation FB-Option selected. TJ = 25°C. –0.6% +0.6%
VFB_Reg2 Feedback Voltage Regulation FB-Option selected. 0°C < TJ < 85°C. –0.65% +0.65%
VFB_Reg3 Feedback Voltage Regulation FB-Option selected. –40°C < TJ < 125°C –0.9% +0.9%
IFB Input leakage current into FB pin Adjustable configuration, VFB = 0.6 V 1 70 nA
Tdelay Start-up delay time IO = 0 mA, time from EN=HIGH until start switching, Adjustable Configuration selected 600 1400 µs
Start-up delay time IO = 0 mA, time from EN=HIGH until start switching, VSET Configuration selected. The typical value is based on the first option of VSET configuration.  650 1850 µs
TSS Soft-Start time IO = 0 mA after Tdelay, from 1st switching pulse until target VO; TR/SS-Pin = OPEN 150 200 µs
ISS SS/TR source current 2.3 2.5 2.7 µA
VFB/VSS/TR Tracking Gain, Adjustable Configuration 0.75
VFB/VSS/TR Tracking Gain tolerance ±8 mV
RDISCH Active Discharge Resistance Discharge = ON - Option Selected, EN = LOW, 7.5 20 Ω