SLVSH49 October   2024 TPSM82916

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Smart Config (S-CONF)
      2. 6.3.2  Device Enable (EN/SYNC)
      3. 6.3.3  Device Synchronization (EN/SYNC)
      4. 6.3.4  Spread Spectrum Modulation
      5. 6.3.5  Output Discharge
      6. 6.3.6  Undervoltage Lockout (UVLO)
      7. 6.3.7  Power-Good Output
      8. 6.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 6.3.9  Current Limit and Short-Circuit Protection
      10. 6.3.10 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Fixed Frequency Pulse Width Modulation
      2. 6.4.2 Low Duty Cycle Operation
      3. 6.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 6.4.4 Second Stage L-C Filter Compensation (Optional)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Custom Design With WEBENCH® Tools
        2. 7.2.2.2 External Component Selection
          1. 7.2.2.2.1 Switching Frequency Selection
          2. 7.2.2.2.2 Output Capacitor Selection
          3. 7.2.2.2.3 Ferrite Bead Selection for Second L-C Filter
          4. 7.2.2.2.4 Input Capacitor Selection
          5. 7.2.2.2.5 Setting the Output Voltage
          6. 7.2.2.2.6 NR/SS Capacitor Selection
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • VCE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TPSM8291x devices are a family of high-efficiency, low noise, and low ripple current mode synchronous buck modules. The devices are designed for noise sensitive applications that normally use an LDO for post regulation such as high-speed ADCs, clock and jitter cleaner, serializer, de-serializer, and radar applications.

To reduce the output voltage ripple, the device loop compensation is designed to operate with an optional second-stage ferrite bead L-C filter. Low-frequency noise levels, similar to a low-noise LDO, are further achieved by filtering the internal voltage reference with a capacitor connected to the NR/SS pin. Combined, these features allow for an output voltage ripple below 10µVRMS.

The device operates at a fixed switching frequency of 2.2MHz, 1.4MHz, or 1MHz, and can be synchronized to an external clock. An optional spread spectrum modulation scheme spreads the DC/DC switching frequency over a wider span, which lowers the mixing spurs.

Device Information
DEVICE NAMEOUTPUT CURRENTPACKAGE(1)PACKAGE SIZE(2)
TPSM829166AVCE (QFN-FCMOD, 16)4.7mm × 4.0mm

TPSM82914(3)

4.5A
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) Product Preview information (not Advance Information).
TPSM82916 Output Noise Versus FrequencyOutput Noise Versus Frequency
TPSM82916 Typical ApplicationTypical Application