SLUSDC9A August   2018  – June 2021 TPSM831D31

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  References: DAC
    7. 6.7  Telemetry
    8. 6.8  Current Sense and Calibration
    9. 6.9  Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET
    10. 6.10 Protections: OVP and UVP
    11. 6.11 Typical Characteristics (VIN = 12 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DCAP+ Control
      2. 7.3.2 Setting the Load-Line (DROOP)
      3. 7.3.3 Start-Up Timing
      4. 7.3.4 Load Transitions
      5. 7.3.5 Switching Frequency
      6. 7.3.6 RESET Function
      7. 7.3.7 VID Table
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation With EN Signal Control
      3. 7.4.3 Operation With OPERATION Control
      4. 7.4.4 Operation With EN and OPERATION Control
    5. 7.5 Programming
      1. 7.5.1  PMBus Connections
      2. 7.5.2  PMBus Address Selection
      3. 7.5.3  Supported Commands
      4. 7.5.4  Commonly Used PMBus Commands
      5. 7.5.5  Voltage, Current, Power, and Temperature Readings
        1. 7.5.5.1 (88h) READ_VIN
        2. 7.5.5.2 (89h) READ_IIN
        3. 7.5.5.3 (8Bh) READ_VOUT
        4. 7.5.5.4 (8Ch) READ_IOUT
        5. 7.5.5.5 (8Dh) READ_TEMPERATURE_1
        6. 7.5.5.6 (96h) READ_POUT
        7. 7.5.5.7 (97h) READ_PIN
        8. 7.5.5.8 (D4h) MFR_SPECIFIC_04
      6. 7.5.6  Output Current Sense and Calibration
        1. 7.5.6.1 Reading Individual Phase Currents
          1. 7.5.6.1.1 Reading Total Current
          2. 7.5.6.1.2 51
      7. 7.5.7  Output Voltage Margin Testing
        1. 7.5.7.1 (01h) OPERATION
        2. 7.5.7.2 (26h) VOUT_MARGIN_LOW
        3. 7.5.7.3 (25h) VOUT_MARGIN_HIGH
      8. 7.5.8  Loop Compensation
        1. 7.5.8.1 (D7h) MFR_SPECIFIC_07
        2. 7.5.8.2 (28h) VOUT_DROOP
      9. 7.5.9  Converter Protection and Response
      10. 7.5.10 Output Overvoltage Protection and Response
        1. 7.5.10.1 (40h) VOUT_OV_FAULT_LIMIT
        2. 7.5.10.2 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.5.11 Maximum Allowed Output Voltage Setting
        1. 7.5.11.1 (24h) VOUT_MAX
      12. 7.5.12 Output Undervoltage Protection and Response
        1. 7.5.12.1 (44h) VOUT_UV_FAULT_LIMIT
        2. 7.5.12.2 (45h) VOUT_UV_FAULT_RESPONSE
      13. 7.5.13 Minimum Allowed Output Voltage Setting
        1. 7.5.13.1 (2Bh) VOUT_MIN
      14. 7.5.14 Output Overcurrent Protection and Response
        1. 7.5.14.1 (46h) IOUT_OC_FAULT_LIMIT
        2. 7.5.14.2 (4Ah) IOUT_OC_WARN_LIMIT
        3. 7.5.14.3 (47h) IOUT_OC_FAULT_RESPONSE
        4. 7.5.14.4 Per Phase Overcurrent Limit Thresholds
      15. 7.5.15 Input Under-Voltage Lockout (UVLO)
        1. 7.5.15.1 (35h) VIN_ON
      16. 7.5.16 Input Over-Voltage Protection and Response
        1. 7.5.16.1 (55h) VIN_OV_FAULT_LIMIT
        2. 7.5.16.2 (56h) VIN_OV_FAULT_RESPONSE
      17. 7.5.17 Input Undervoltage Protection and Response
        1. 7.5.17.1 (59h) VIN_UV_FAULT_LIMIT
        2. 7.5.17.2 (5Ah) VIN_UV_FAULT_RESPONSE
      18. 7.5.18 Input Overcurrent Protection and Response
        1. 7.5.18.1 (5Bh) IIN_OC_FAULT_LIMIT
        2. 7.5.18.2 (5Dh) IIN_OC_WARN_LIMIT
        3. 7.5.18.3 (5Ch) IIN_OC_FAULT_RESPONSE
      19. 7.5.19 Overtemperature Protection and Response
        1. 7.5.19.1 (4Fh) OT_FAULT_LIMIT
        2. 7.5.19.2 (51h) OT_WARN_LIMIT
        3. 7.5.19.3 (50h) OT_FAULT_RESPONSE
      20. 7.5.20 Dynamic Phase Shedding (DPS)
        1. 7.5.20.1 (DEh) MFR_SPECIFIC_14
        2. 7.5.20.2 (DFh) MFR_SPECIFIC_15
      21. 7.5.21 NVM Programming
      22. 7.5.22 NVM Security
        1. 7.5.22.1 (FAh) MFR_SPECIFIC_42
      23. 7.5.23 Black Box Recording
        1. 7.5.23.1 (D8h) MFR_SPECIFIC_08
      24. 7.5.24 Board Identification and Inventory Tracking
      25. 7.5.25 Status Reporting
        1. 7.5.25.1 (78h) STATUS_BYTE
        2. 7.5.25.2 (79h) STATUS_WORD
        3. 7.5.25.3 (7Ah) STATUS_VOUT
        4. 7.5.25.4 (7Bh) STATUS_IOUT
        5. 7.5.25.5 (7Ch) STATUS_INPUT
        6. 7.5.25.6 (7Dh) STATUS_TEMPERATURE
        7. 7.5.25.7 (7Eh) STATUS_CML
        8. 7.5.25.8 (80h) STATUS_MFR_SPECIFIC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitors
        2. 8.2.2.2 Output Capacitors
        3. 8.2.2.3 Switching Frequency
        4. 8.2.2.4 Set PMBus Address
        5. 8.2.2.5 PMBus GUI Default Values
      3. 8.2.3 Application Performance Plots
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • MOA|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2 PMBus Address Selection

The PMBus slave address is set by the voltage on the ADDR pin and is selected with a resistor from the ADDR pin to GND. Refer to Table 7-5.

Note that TPSM831D31 uses 7 bit addressing, per the SMBus specification. Users communicating to the device using generic I2C drivers should be aware that these 7 bits occupy the most significant bits of the first byte in each transaction, with the least significant bit being the data direction bit (0 for write operations, 1 for read operations). That is, for read transactions, the address byte is A6A5A4A3A2A1A01 and for write operations the address byte is A6A5A4A3A2A1A00. Refer to the SMBus specification for more information.

Table 7-5 PMBus Slave Address Selection
VADDR (V)PMBus Address
(7 bit binary)
A6A5A4A3A2A1A0		PMBus Address
(7 bit decimal)		RADDRL (kΩ)I2C Address Byte
(Write Operation)		I2C Address Byte
(Read Operation)
≤ 0.039 V1011000b88d0B0hB1h
0.073 V ± 15 mV1011001b89d0.453B2hB3h
0.122 V ± 15 mV1011010b90d0.768B4hB5h
0.171 V ± 15 mV1011011b91d1.13B6hB7h
0.219 V ± 15 mV1011100b92d1.47B8hB9h
0.268 V ± 15 mV1011101b93d1.87BAhBBh
0.317 V ± 15 mV1011110b94d2.32BChBDh
0.366 V ± 15 mV1011111b95d2.74BEhBFh
0.415 V ± 15 mV1100000b96d3.24C0hC1h
0.464 V ± 15 mV1100001b97d3.74C2hC3h
0.513 V ± 15 mV1100010b98d4.32C4hC5h
0.562 V ± 15 mV1100011b99d4.99C6hC7h
0.610 V ± 15 mV1100100b100d5.62C8hC9h
0.660 V ± 15 mV1100101b101d6.34CAhCBh
0.708 V ± 15 mV1100110b102d7.15CChCDh
0.757 V ± 15 mV1100111b103d8.06CEhCFh
0.806 V ± 15 mV1101000b104d9.09D0hD1h
0.854 V ± 15 mV1101001b105d10.0D2hD3h
0.903 V ± 15 mV1101010b106d11.3D4hD5h
0.952 V ± 15 mV1101011b107d12.7D6hD7h
1.000 V ± 15 mV1101100b108d14.3D8hD9h
1.050 V ± 15 mV1101101b109d16.2DAhDBh
1.098 V ± 15 mV1101110b110d18.2DChDDh
1.147 V ± 15 mV1101111b111d20.5DEhDFh
1.196 V ± 15 mV1110000b112d23.7E0hE1h
1.245 V ± 15 mV1110001b113d27.4E2hE3h
1.294 V ± 15 mV1110010b114d31.6E4hE5h
1.343 V ± 15 mV1110011b115d37.4E6hE7h
1.392 V ± 15 mV1110100b116d45.3E8hE9h
1.440 V ± 15 mV1110101b117d54.9EAhEBh
1.489 V ± 15 mV1110110b118d69.8EChEDh
1.540 V ± 15 mV1110111b119d95.3EEhEFh