SLUSDC9A
August 2018 – June 2021
TPSM831D31
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
References: DAC
6.7
Telemetry
6.8
Current Sense and Calibration
6.9
Logic Interface Pins: A_EN, A_PGOOD, B_EN, B_PGOOD,RESET
6.10
Protections: OVP and UVP
6.11
Typical Characteristics (VIN = 12 V)
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
DCAP+ Control
7.3.2
Setting the Load-Line (DROOP)
7.3.3
Start-Up Timing
7.3.4
Load Transitions
7.3.5
Switching Frequency
7.3.6
RESET Function
7.3.7
VID Table
7.4
Device Functional Modes
7.4.1
Continuous Conduction Mode
7.4.2
Operation With EN Signal Control
7.4.3
Operation With OPERATION Control
7.4.4
Operation With EN and OPERATION Control
7.5
Programming
7.5.1
PMBus Connections
7.5.2
PMBus Address Selection
7.5.3
Supported Commands
7.5.4
Commonly Used PMBus Commands
7.5.5
Voltage, Current, Power, and Temperature Readings
7.5.5.1
(88h) READ_VIN
7.5.5.2
(89h) READ_IIN
7.5.5.3
(8Bh) READ_VOUT
7.5.5.4
(8Ch) READ_IOUT
7.5.5.5
(8Dh) READ_TEMPERATURE_1
7.5.5.6
(96h) READ_POUT
7.5.5.7
(97h) READ_PIN
7.5.5.8
(D4h) MFR_SPECIFIC_04
7.5.6
Output Current Sense and Calibration
7.5.6.1
Reading Individual Phase Currents
7.5.6.1.1
Reading Total Current
7.5.6.1.2
51
7.5.7
Output Voltage Margin Testing
7.5.7.1
(01h) OPERATION
7.5.7.2
(26h) VOUT_MARGIN_LOW
7.5.7.3
(25h) VOUT_MARGIN_HIGH
7.5.8
Loop Compensation
7.5.8.1
(D7h) MFR_SPECIFIC_07
7.5.8.2
(28h) VOUT_DROOP
7.5.9
Converter Protection and Response
7.5.10
Output Overvoltage Protection and Response
7.5.10.1
(40h) VOUT_OV_FAULT_LIMIT
7.5.10.2
(41h) VOUT_OV_FAULT_RESPONSE
7.5.11
Maximum Allowed Output Voltage Setting
7.5.11.1
(24h) VOUT_MAX
7.5.12
Output Undervoltage Protection and Response
7.5.12.1
(44h) VOUT_UV_FAULT_LIMIT
7.5.12.2
(45h) VOUT_UV_FAULT_RESPONSE
7.5.13
Minimum Allowed Output Voltage Setting
7.5.13.1
(2Bh) VOUT_MIN
7.5.14
Output Overcurrent Protection and Response
7.5.14.1
(46h) IOUT_OC_FAULT_LIMIT
7.5.14.2
(4Ah) IOUT_OC_WARN_LIMIT
7.5.14.3
(47h) IOUT_OC_FAULT_RESPONSE
7.5.14.4
Per Phase Overcurrent Limit Thresholds
7.5.15
Input Under-Voltage Lockout (UVLO)
7.5.15.1
(35h) VIN_ON
7.5.16
Input Over-Voltage Protection and Response
7.5.16.1
(55h) VIN_OV_FAULT_LIMIT
7.5.16.2
(56h) VIN_OV_FAULT_RESPONSE
7.5.17
Input Undervoltage Protection and Response
7.5.17.1
(59h) VIN_UV_FAULT_LIMIT
7.5.17.2
(5Ah) VIN_UV_FAULT_RESPONSE
7.5.18
Input Overcurrent Protection and Response
7.5.18.1
(5Bh) IIN_OC_FAULT_LIMIT
7.5.18.2
(5Dh) IIN_OC_WARN_LIMIT
7.5.18.3
(5Ch) IIN_OC_FAULT_RESPONSE
7.5.19
Overtemperature Protection and Response
7.5.19.1
(4Fh) OT_FAULT_LIMIT
7.5.19.2
(51h) OT_WARN_LIMIT
7.5.19.3
(50h) OT_FAULT_RESPONSE
7.5.20
Dynamic Phase Shedding (DPS)
7.5.20.1
(DEh) MFR_SPECIFIC_14
7.5.20.2
(DFh) MFR_SPECIFIC_15
7.5.21
NVM Programming
7.5.22
NVM Security
7.5.22.1
(FAh) MFR_SPECIFIC_42
7.5.23
Black Box Recording
7.5.23.1
(D8h) MFR_SPECIFIC_08
7.5.24
Board Identification and Inventory Tracking
7.5.25
Status Reporting
7.5.25.1
(78h) STATUS_BYTE
7.5.25.2
(79h) STATUS_WORD
7.5.25.3
(7Ah) STATUS_VOUT
7.5.25.4
(7Bh) STATUS_IOUT
7.5.25.5
(7Ch) STATUS_INPUT
7.5.25.6
(7Dh) STATUS_TEMPERATURE
7.5.25.7
(7Eh) STATUS_CML
7.5.25.8
(80h) STATUS_MFR_SPECIFIC
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.2.1
Input Capacitors
8.2.2.2
Output Capacitors
8.2.2.3
Switching Frequency
8.2.2.4
Set PMBus Address
8.2.2.5
PMBus GUI Default Values
8.2.3
Application Performance Plots
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Examples
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
MOA|28
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slusdc9a_oa
2
Applications
High-performance processor / ASIC with dual power rails
Networking processor power (
Broadcom®
,
Cavium®
,
Marvell®
,
NXP®
)
High-current FPGA power (
Intel®
,
Xilinx®
)
High-performance ARM processor power