SLUSCV7A July   2017  – August 2017 TPSM84203 , TPSM84205 , TPSM84212

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 ESD Ratings
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics (VOUT = 3.3 V)
    8. 6.8 Typical Characteristics (VOUT = 5 V)
    9. 6.9 Typical Characteristics (VOUT = 12 V)
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Capacitors
      2. 7.3.2 Output Capacitors
      3. 7.3.3 Drop-Out Voltage
      4. 7.3.4 Internal Soft-Start
      5. 7.3.5 Safe Startup into Pre-Biased Outputs
      6. 7.3.6 Over-Current Protection
      7. 7.3.7 Output Over-Voltage Protection
      8. 7.3.8 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Eco-mode Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Input and Output Capacitors
      3. 8.2.3 Application Curves
        1. 8.2.3.1 EMI
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 28 shows a typical PCB layout. Some considerations for an optimized layout are:

  • Use large copper areas for power planes (VIN, VOUT, and GND) to minimize conduction loss and thermal stress.
  • Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
  • Locate additional output capacitors between the ceramic capacitor and the load.
  • Use multiple vias to connect the power planes to internal layers.

10.2 Layout Example

TPSM84203 TPSM84205 TPSM84212 Layout2.gif Figure 28.