SLUSEU0A October   2023  – December 2023 TPSM843320

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics (Module)
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  VIN Pins and VIN UVLO
      2. 6.3.2  Enable and Adjustable UVLO
      3. 6.3.3  Adjusting the Output Voltage
      4. 6.3.4  Switching Frequency Selection
      5. 6.3.5  Switching Frequency Synchronization to an External Clock
        1. 6.3.5.1 Internal PWM Oscillator Frequency
        2. 6.3.5.2 Loss of Synchronization
        3. 6.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 6.3.6  Ramp Amplitude Selection
      7. 6.3.7  Soft Start and Prebiased Output Start-Up
      8. 6.3.8  Mode Pin
      9. 6.3.9  Power Good (PGOOD)
      10. 6.3.10 Current Protection
        1. 6.3.10.1 Positive Inductor Current Protection
        2. 6.3.10.2 Negative Inductor Current Protection
      11. 6.3.11 Output Overvoltage and Undervoltage Protection
      12. 6.3.12 Overtemperature Protection
      13. 6.3.13 Output Voltage Discharge
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Discontinuous Conduction Mode During Soft Start
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 1.0V Output, 1MHz Application
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1  Switching Frequency
          2. 7.2.1.2.2  Output Inductor Selection
          3. 7.2.1.2.3  Output Capacitor
          4. 7.2.1.2.4  Input Capacitor
          5. 7.2.1.2.5  Adjustable Undervoltage Lockout
          6. 7.2.1.2.6  Output Voltage Resistors Selection
          7. 7.2.1.2.7  Bootstrap Capacitor Selection
          8. 7.2.1.2.8  BP5 Capacitor Selection
          9. 7.2.1.2.9  PGOOD Pullup Resistor
          10. 7.2.1.2.10 Current Limit Selection
          11. 7.2.1.2.11 Soft-Start Time Selection
          12. 7.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 7.2.1.2.13 MODE Pin
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.2.1.2.12 Ramp Selection and Control Loop Stability

The MODE pin is used to select between three different ramp settings. The most optimal ramp setting depends on VOUT, fSW, LOUT, and COUT. To get started, calculate LC double pole frequency using Equation 15. The ratio between fSW and fLC must then be calculated. Based on this ratio and the output voltage, the recommended ramp setting must be selected using Figure 7-3. With a 1V output, TI recommends the 1pF ramp for ratios between approximately 35 and 58, TI recommends the 2pF ramp for ratios between approximately 58 and 86, and TI recommends the 4pF ramp for ratios greater than approximately 86. In general, use the largest ramp capacitor the design supports. Increasing the ramp capacitor improves transient response but can reduce stability margin or increase on-time jitter.

For this design, fLC is 8.54kHz and the ratio is 117 which is in the 4-pF ramp setting. Through bench evaluation, the design having sufficient stability margin with the 4pF ramp was discovered, so this setting was selected for the best transient response. The recommended ramp settings given by Figure 7-3 include margin to account for potential component tolerances and variations across operating conditions, using a higher ramp setting as shown in this example is possible.

Equation 15. TPSM843320
TPSM843320 Recommended Ramp SettingsFigure 7-3 Recommended Ramp Settings

Use a feedforward capacitor (CFF) in parallel with the upper feedback resistor (RFBT) to add a zero into the control loop to provide phase boost. Include a placeholder for this capacitor as the zero this capacitor provides can be required to meet phase margin requirements. This capacitor also adds a pole at a higher frequency than the zero. The pole and zero frequency are not independent so as a result, after the zero location is chosen, the pole is fixed as well. The zero is placed at 1/4 the fSW by calculating the value of CFF with Equation 16. The calculated value is 64pF.

Using bench measurements of the AC response, the feedforward capacitor for this example design was increased to 100pF to improve the transient response.

Equation 16. TPSM843320

Using larger feedforward capacitors to further improve the transient response but take care to make sure there is a minimum of –9dB gain margin in all operating conditions is possible. The feedforward capacitor injects noise on the output into the FB pin. This added noise can result in increased on-time jitter at the switching node. Too little gain margin can cause a repeated wide and narrow pulse behavior. Adding a 499Ω resistor in series with the feedforward capacitor can help reduce the impact of noise on the FB pin in case of non-ideal PCB layout. The value of this resistor must be kept small as larger values bring the feedforward pole and zero closer together degrading the phase boost the feedforward capacitor provides.

When using higher ESR output capacitors, such as polymer or tantalum, the ESR zero (fESR) must be accounted for. The ESR zero can be calculated using Equation 17. If the ESR zero frequency is less than the estimated bandwidth of 1/10th the fSW, the gain margin and phase margin are affected. A series R-C from the FB pin to ground can be used to add a pole into the control loop if necessary. All ceramic capacitors are used in this design so the effect of the ESR zero is ignored.

Equation 17. TPSM843320