The MODE pin is used to select between three different ramp settings. The most optimal ramp setting depends on V_OUT, f_SW, L_OUT, and C_OUT. To get started, calculate LC double pole frequency using Equation 15. The ratio between f_SW and f_LC must then be calculated. Based on this ratio and the output voltage, the recommended ramp setting must be selected using Figure 7-3. With a 1V output, TI recommends the 1pF ramp for ratios between approximately 35 and 58, TI recommends the 2pF ramp for ratios between approximately 58 and 86, and TI recommends the 4pF ramp for ratios greater than approximately 86. In general, use the largest ramp capacitor the design supports. Increasing the ramp capacitor improves transient response but can reduce stability margin or increase on-time jitter.

For this design, f_LC is 18.2kHz and the ratio is 55 which is on the border of the 1pF and 2pF ramp settings. Through bench evaluation, the design having sufficient stability margin with the 2pF ramp was discovered, so this setting was selected for the best transient response. The recommended ramp settings given by Figure 7-3 include margin to account for potential component tolerances and variations across operating conditions, using a higher ramp setting as shown in this example is possible.

Equation 15.

Figure 7-3 Recommended Ramp Settings

Use a feedforward capacitor (C_FF) in parallel with the upper feedback resistor (R_FBT) to add a zero into the control loop to provide phase boost. Include a placeholder for this capacitor as the zero this capacitor provides can be required to meet phase margin requirements. This capacitor also adds a pole at a higher frequency than the zero. The pole and zero frequency are not independent so as a result, after the zero location is chosen, the pole is fixed as well. The zero is placed at 1/4 the f_SW by calculating the value of C_FF with Equation 16. The calculated value is 42pF.

Equation 16.

Using larger feedforward capacitors to further improve the transient response but take care to make sure there is a minimum of –9dB gain margin in all operating conditions is possible. The feedforward capacitor injects noise on the output into the FB pin. This added noise can result in increased on-time jitter at the switching node. Too little gain margin can cause a repeated wide and narrow pulse behavior. Adding a 499Ω resistor in series with the feedforward capacitor can help reduce the impact of noise on the FB pin in case of non-ideal PCB layout. The value of this resistor must be kept small as larger values bring the feedforward pole and zero closer together degrading the phase boost the feedforward capacitor provides.

When using higher ESR output capacitors, such as polymer or tantalum, the ESR zero (f_ESR) must be accounted for. The ESR zero can be calculated using Equation 17. If the ESR zero frequency is less than the estimated bandwidth of 1/10th the f_SW, the gain margin and phase margin are affected. A series R-C from the FB pin to ground can be used to add a pole into the control loop if necessary. All ceramic capacitors are used in this design so the effect of the ESR zero is ignored.

Equation 17.