SLUSFE1 august   2023 TPSM843A22E

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN Pins and VIN UVLO
      2. 7.3.2  Internal Bypassing (BP5)
      3. 7.3.3  Enable and Adjustable UVLO
        1. 7.3.3.1 Internal Sequence of Events During Start-up
      4. 7.3.4  Switching Frequency Selection
      5. 7.3.5  Switching Frequency Synchronization to an External Clock
        1. 7.3.5.1 Internal PWM Oscillator Frequency
        2. 7.3.5.2 Loss of Synchronization
        3. 7.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 7.3.6  Remote Sense Amplifier and Adjusting the Output Voltage
      7. 7.3.7  Loop Compensation Guidelines
        1. 7.3.7.1 Output Filter Inductor Tradeoffs
        2. 7.3.7.2 Ramp Capacitor Selection
        3. 7.3.7.3 Output Capacitor Selection
        4. 7.3.7.4 Design Method for Good Transient Response
      8. 7.3.8  Soft Start and Prebiased Output Start-up
      9. 7.3.9  MSEL Pin
      10. 7.3.10 Power Good (PG)
      11. 7.3.11 Output Overload Protection
        1. 7.3.11.1 Positive Inductor Current Protection
        2. 7.3.11.2 Negative Inductor Current Protection
      12. 7.3.12 Output Overvoltage and Undervoltage Protection
      13. 7.3.13 Overtemperature Protection
      14. 7.3.14 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Discontinuous Conduction Mode During Soft Start
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.0-V Output, 1-MHz Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Input Capacitor
          5. 8.2.1.2.5  Adjustable Undervoltage Lockout
          6. 8.2.1.2.6  Output Voltage Resistors Selection
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  BP5 Capacitor Selection
          9. 8.2.1.2.9  PG Pullup Resistor
          10. 8.2.1.2.10 Current Limit Selection
          11. 8.2.1.2.11 Soft-Start Time Selection
          12. 8.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 8.2.1.2.13 MSEL Pin
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Performance
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

TJ = –55°C to +125°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA
ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 20 32 µA
VINUVLO(R) VIN UVLO rising threshold VIN rising 3.8 4.00 4.2 V
VINUVLO(H) VIN UVLO hysteresis 150 mV
INTERNAL LDO
BP5 Internal LDO output voltage VVIN = 12 V, IVBP5 = 25 mA 4.5 V
Internal LDO dropout voltage VVIN – VVBP5, VVIN = 3.8 V, IVBP5 = 25 mA 350 mV
Internal LDO short-circuit current limit VVIN = 12 V 177 mA
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V
VEN(F) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V
VEN(H) EN voltage hysteresis 100 mV
EN pin sourcing current VEN = 1.1 V 1.5 µA
EN pin sourcing current VEN = 1.3 V 11.6 µA
REFERENCE VOLTAGE
IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA
REMOTE SENSE AMPLIFIER
ILEAK(GOSNS) Current out of GOSNS pin 85 90 95 µA
VIRNG(GOSNS) GOSNS common mode voltage for regulation AGND +/- VGOSNS –100 100 mV
SWITCHING FREQUENCY AND OSCILLATOR
fSW Switching frequency RFSEL = 24.3 kΩ to AGND  450 500 550 kHz
fSW Switching frequency RFSEL = 17.4 kΩ to AGND  675 750 825 kHz
fSW Switching frequency RFSEL = 11.8 kΩ to AGND  900 1000 1100 kHz
fSW Switching frequency RFSEL = 8.06 kΩ to AGND  1350 1500 1650 kHz
fSW Switching frequency RFSEL = 4.99 kΩ to AGND  1980 2200 2420 kHz
SYNCHRONIZATION
VIH(sync) High-level input voltage 1.8 V
VIL(sync) Low-level input voltage 0.8 V
SOFT-START
tSS1 Soft-start time RMSEL = 1.78 kΩ 1 ms
tSS2 Soft-start time RMSEL = 2.21 kΩ 2 ms
tSS3 Soft-start time RMSEL = 2.74 kΩ 4 ms
tSS4 Soft-start time RMSEL = 3.32 kΩ 8 ms
POWER STAGE
RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 6.5 mΩ
RDS(on)LS Low-side MOSFET on-resistance TJ = 25°C, VBP5 = 4.5 V 2.0 mΩ
VVIN(TH_r) VIN throttle rising threshold TJ = 25°C. Weaken high-side gate drive upon VIN rising 16 V
VVIN(TH_f) VIN throttle falling threshold TJ = 25°C. Recover high-side gate drive upon VIN falling 15.5 V
VBOOT-SW(UV_R) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V
VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V
TON(min) Minimum ON pulse width 22 37 ns
TOFF(min) Minimum OFF pulse width (1) 115 ns
CURRENT SENSE AND OVERCURRENT PROTECTION
IHS(OC1) High-side peak current limit (A22) RMSEL = 2.1 kΩ 15.75 17.5 19.25 A
ILS(OC1) Low-side valley current limit (A22) RMSEL = 2.1 kΩ 11.88 13.2 14.52 A
ILS(NOC) Low-side negative current limit Current into SW pin 7 A
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS
VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF
VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF
PG (Power Good)
PG threshold VFB rising (Good) 88 92 94 % VREF
PG threshold VFB rising (OV Fault) 112 116 118 % VREF
PG threshold VFB falling (Good) 103.5 108 109.5 % VREF
PG threshold VFB falling (UV Fault) 79 84 85 % VREF
IPG(LKG) Leakage current into PG pin when open drain output is high VPG = 4.7 V 5 µA
VPG(low) PG low-level output voltage IPG = 2 mA, VIN = 12 V 0.5 V
Min VIN for valid PG output 1 V
PG delay going from low to high 256 us
PG delay going from high to low 8 µs
HICCUP
Hiccup time before re-start 7*tSS ms
OUTPUT DISCHARGE
RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising 165 °C
TJ(HYS) Thermal shutdown hysteresis (1) 30 °C
(1) Specified by design