SLVSDF7A December   2016  – July 2017 TPSM84A21

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Transient Response
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Package Specifications
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Adjusting the Output Voltage (VADJ)
      2. 7.3.2  Input and Output Capacitance
      3. 7.3.3  Transient Response
        1. 7.3.3.1 Transient Response Waveforms
      4. 7.3.4  Oscillator Frequency
      5. 7.3.5  External Clock Syncronization
      6. 7.3.6  Soft Start
      7. 7.3.7  Power Good (PGOOD)
      8. 7.3.8  Gate Driver (VG)
      9. 7.3.9  Startup into Pre-biased Outputs
      10. 7.3.10 Thermal Shutdown
      11. 7.3.11 Overcurrent Protection
      12. 7.3.12 Output Undervoltage/Overvoltage Protection
      13. 7.3.13 Enable (EN)
      14. 7.3.14 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Active Mode
      2. 7.4.2 Light Load Operation
      3. 7.4.3 Shutdown Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Setting the Output Voltage
        2. 8.2.2.2 Input and Output Capacitance
        3. 8.2.2.3 Power Good (PGOOD)
        4. 8.2.2.4 External VG Voltage
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
    3. 10.3 EMI
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.14 Undervoltage Lockout (UVLO)

The TPSM84A21 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 7.65 V(max) with a typical hysteresis of 250 mV.

If an application requires a higher UVLO threshold, the UVLO pin can be configured as shown in Figure 16. The value of RUVLO1 and RUVLO2 can be calculated using Equation 3 and Equation 4 or selected from Table 2. It is recommended to set the UVLO hysteresis of approximately 500mV in order to avoid repeated chatter during start up or shut down. Table 2 shows recommended RUVLO1 and RUVLO2 values for various VIN UVLO rising thresholds, with 500 mV of hysteresis.

Equation 3. TPSM84A21 EQUVLOA1.gif
Equation 4. TPSM84A21 EQUVLOA2.gif
TPSM84A21 EaglesUVLO.gifFigure 16. Adjustable UVLO

Table 2. Standard Resistor Values For Adjusting VIN UVLO

VIN UVLO RISING THRESHOLD (V) 8.0 8.5 9.0 9.5 10.0
VIN UVLO FALLING THRESHOLD (V) 7.5 8.0 8.5 9.0 9.5
RUVLO1 (kΩ) 169 169 169 169 169
RUVLO2 (kΩ) 29.4 27.4 25.5 24.3 22.6