SLUSFD2B September   2023  – March 2024 TPSM861252 , TPSM861253 , TPSM861257

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Family Devices
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PWM Operation and D-CAP3™ Control Mode
      2. 7.3.2 Eco-mode Control
      3. 7.3.3 Soft Start and Prebiased Soft Start
      4. 7.3.4 Overvoltage Protection
      5. 7.3.5 Frequency
      6. 7.3.6 Large Duty Operation
      7. 7.3.7 Current Protection and Undervoltage Protection
      8. 7.3.8 Undervoltage Lockout (UVLO) Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Eco-mode Operation
      2. 7.4.2 FCCM Mode Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design with WEBENCH® Tools
        2. 8.2.2.2 Output Voltage Resistors Selection
        3. 8.2.2.3 Output Filter Selection
        4. 8.2.2.4 Input Capacitor Selection
        5. 8.2.2.5 Enable Circuit
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Custom Design with WEBENCH® Tools
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over operating TJ = –40oC – 125oC, VVIN = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY VOLTAGE
VIN Input voltage range VIN 3 17 V
IVIN VIN supply current No load, VEN = 5V, non-switching, ECO version 100 µA
IVIN VIN supply current No load, VEN = 5V, non-switching, FCCM version 370 µA
IINSDN VIN shutdown current No load, VEN = 0V 2 µA
UVLO
UVLO VIN undervoltage lockout Wake up VIN voltage 2.8 2.9 3.0 V
UVLO VIN undervoltage lockout Shut down VIN voltage 2.6 2.7 2.8 V
UVLO VIN undervoltage lockout Hysteresis VIN voltage 200 mV
FEEDBACK VOLTAGE
VFB FB voltage TJ = 25°C 594 600 606 mV
VFB FB voltage TJ = –40°C to 125°C 591 600 609 mV
VOUT TPSM861253 output voltage TJ = 0°C to 65°C 3.27 3.3 3.33 V
VOUT TPSM861253 output voltage TJ = –40°C to 125°C 3.25 3.3 3.35 V
MOSFET
RDS (ON)HI High-side MOSFET Rds(on) TJ = 25°C, VVIN ≥ 5V 55 mΩ
TJ = 25°C, VVIN = 3V (1) 68 mΩ
RDS (ON)LO Low-side MOSFET Rds(on) TJ = 25°C,VVIN ≥ 5V 24 mΩ
TJ = 25°C, VVIN = 3V (1) 30 mΩ
DUTY CYCLE and FREQUENCY CONTROL
FSW Switching frequency TJ = 25°C, VVOUT = 3.3V 1.4 MHz
TOFF(MIN)(1) Minimum off-time VFB = 0.5V 110 ns
TON(MIN) Minimum on-time 60 ns
CURRENT LIMIT
IOCL_LS Over current threshold Valley current set point for TPSM861252 and TPSM861257 1.5 2.3 3.1 A
IOCL_LS Over current threshold Valley current set point for TPSM861253 1.5 2.3 2.9 A
INOCL Negative over current threshold Valley current set point 1.5 2.0 2.5 A
LOGIC THRESHOLD
VEN(ON) EN threshold high-level 1.15 1.20 1.25 V
VEN(OFF) EN threshold low-level 0.90 1.00 1.10 V
VENHYS EN hystersis 200 mV
REN1 EN pulldown resister 2 MΩ
OUTPUT DISCHARGE and SOFT START
tSS Internal soft-start time 1.6 ms
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP OVP trip threshold 110 115 120 %
tOVPDLY OVP prop deglitch 24 us
VUVP UVP trip threshold 55 60 65 %
tUVPDLY UVP prop deglitch 220 us
tUVPEN Output hiccup enable delay relative to
SS time		 UVP detect 14 ms
PGOOD
TPGDLY PG start-up delay PG from low to high 1 ms
TPGDLY PG start-up delay PG from high to low 28 us
VPGTH PG threshold VFB falling (fault) 80 85 90 %
VPGTH PG threshold VFB rising (good) 85 90 95 %
VPGTH PG threshold VFB rising (fault) 110 115 120 %
VPGTH PG threshold VFB falling (good) 105 110 115 %
VPG_L PG sink current capability IOL = 4mA 0.4 V
IPGLK PG leak current VPgood = 5.5V 1 uA
THERMAL PROTECTION
TOTP(1) OTP trip threshold 155 °C
TOTPHSY(1) OTP hysteresis 20 °C
(1) Specified by design