SLVSH20B October   2023  – May 2024 TPSM86837 , TPSM86838

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  The Adaptive On-Time Control and PWM Operation
      2. 6.3.2  Mode Selection
        1. 6.3.2.1 FCCM Control and Eco-mode Control
      3. 6.3.3  Soft Start and Prebiased Soft Start
      4. 6.3.4  Enable and Adjusting Undervoltage Lockout
      5. 6.3.5  Output Overcurrent Limit and Undervoltage Protection
      6. 6.3.6  Overvoltage Protection
      7. 6.3.7  UVLO Protection
      8. 6.3.8  Thermal Shutdown
      9. 6.3.9  Output Voltage Discharge
      10. 6.3.10 Power Good
      11. 6.3.11 Large Duty Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Operation
      2. 6.4.2 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Resistors Selection
        2. 7.2.2.2 Output Filter Selection
        3. 7.2.2.3 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Application Thermal Considerations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TPSM86837 TPSM86838 19-Pin B3QFN RCG Package (Top View)Figure 4-1 19-Pin B3QFN RCG Package (Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.

VOUT

1, 16

O

Output voltage. These pins are connected to the internal buck inductor. Connect these pins to the output load and connect external output capacitors between these pins and PGND.

MODE

2

I

Switching frequency selection pin. Connect this pin to a resistor to AGND for different switching frequency options shown in Table 6-1.

EN

3

I

Enable input control. Driving EN high or leaving this pin floating enables the module. A resistor divider can be used to imply an UVLO function.

FB

4

I

Feedback input. Connect the midpoint of the feedback resistor divider to this pin. Connect the upper resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower resistor (RFBB) of the feedback divider to AGND. Do not leave open or connect to ground.

AGND

5

G

Ground of internal analog circuitry. Connect AGND to PGND plane at a single point.

PG

6

O

Open-drain power-good monitor output that asserts low if the output voltage is out of PG threshold due to overvoltage, undervoltage, thermal shutdown, EN shutdown, or during soft start.

SS

7

I

Soft-start time selection pin. Connecting an external capacitor to AGND to set the soft-start time. A minimum 22nF ceramic capacitor must be connected at this pin, which sets the minimum soft-start time to approximately 2.2ms. Do not float.

VIN

8, 9

P

Input supply voltage. A 100nF input capacitor is internally connected from this pin to PGND within the module. Externally, connect input capacitors between these pins and PGND in close proximity to the device.

SW

10, 11

O

Switching node. Do not place any external component on this pin or connect to any signal. The amount of copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI.

BOOT

12

I/O

Bootstrap pin for the internal high-side gate driver. A 100nF bootstrap capacitor is internally connected from this pin to SW within the module to provide the bootstrap voltage. Do not place any external component on this pin or connect to any signal.

NC

13, 14, 15

—

No connection. Tie to GND for better thermal performance.

PGND

17, 18, 19

G

Power ground. This pin is the return current path for the power stage of the device. Connect these pads to the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins.
(1) I = input, O = output, G = ground, P = power