SLVSH20B October   2023  – May 2024 TPSM86837 , TPSM86838

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  The Adaptive On-Time Control and PWM Operation
      2. 6.3.2  Mode Selection
        1. 6.3.2.1 FCCM Control and Eco-mode Control
      3. 6.3.3  Soft Start and Prebiased Soft Start
      4. 6.3.4  Enable and Adjusting Undervoltage Lockout
      5. 6.3.5  Output Overcurrent Limit and Undervoltage Protection
      6. 6.3.6  Overvoltage Protection
      7. 6.3.7  UVLO Protection
      8. 6.3.8  Thermal Shutdown
      9. 6.3.9  Output Voltage Discharge
      10. 6.3.10 Power Good
      11. 6.3.11 Large Duty Operation
    4. 6.4 Device Functional Modes
      1. 6.4.1 Standby Operation
      2. 6.4.2 Light Load Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Resistors Selection
        2. 7.2.2.2 Output Filter Selection
        3. 7.2.2.3 Input Capacitor Selection
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Application Thermal Considerations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

The following list summarizes the essential guidelines for PCB layout and component placement to optimize DC/DC module performance, including thermals and EMI signature.

  1. Use a four-layer PCB with two-ounce copper thickness for good thermal performance and with maximum ground plane.
  2. Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement of the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package. The high-frequency currents are split in two and effectively flow in opposing directions such that the related magnetic fields contributions cancel each other, leading to improved EMI performance.
    • Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric.
    • Make ground return paths for the input capacitors consist of localized top-side planes that connect to the PGND pads under the module.
    • Make VIN traces as wide as possible to reduce trace impedance. The wide areas are also of advantage from the view point of heat dissipation. Even though the VIN pins are connected internally, use a wide polygon plane on a bottom PCB layer to connect these pins together and to the input supply.
  3. Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement of the output capacitors enables magnetic field cancellation and EMI mitigation.
    • Make ground return paths for the output capacitors consist of localized top-side planes that connect to the PGND pads under the module.
    • Make VOUT traces as wide as possible to reduce trace impedance. The wide areas are also of advantage from the view point of heat dissipation. Even though the VOUT pins are connected internally, use a wide polygon plane on a bottom PCB layer to connect these pins together and to the load, thus reducing conduction loss and thermal stress.
  4. Keep the FB trace as short as possible by placing the feedback resistors close to the FB pin. Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. FB is the input to the voltage-loop error amplifier and represents a high-impedance node sensitive to noise. Route a trace from the upper feedback resistor to the required point of output voltage regulation. Place the voltage feedback loop away from the high-voltage switching trace, and preferably has ground shield.
  5. Provide enough PCB area for proper heatsinking. Use sufficient copper area to achieve a low thermal impedance commensurate with the maximum load current and ambient temperature conditions. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pads (PGND) of the package to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes.