SLUSEJ1A December   2021  – November 2023 TPSM8D6C24

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Average Current-Mode Control
        1. 6.3.1.1 On-Time Modulator
        2. 6.3.1.2 Current Error Integrator
        3. 6.3.1.3 Voltage Error Integrator
      2. 6.3.2  Linear Regulators
      3. 6.3.3  AVIN and PVIN Pins
      4. 6.3.4  Input Undervoltage Lockout (UVLO)
        1. 6.3.4.1 Fixed AVIN UVLO
        2. 6.3.4.2 Fixed VDD5 UVLO
        3. 6.3.4.3 Programmable PVIN UVLO
        4. 6.3.4.4 EN/UVLO Pin
      5. 6.3.5  Start-Up and Shutdown
      6. 6.3.6  Differential Sense Amplifier and Feedback Divider
      7. 6.3.7  Set Output Voltage and Adaptive Voltage Scaling (AVS)
        1. 6.3.7.1 Reset Output Voltage
        2. 6.3.7.2 Soft Start
      8. 6.3.8  Prebiased Output Start-Up
      9. 6.3.9  Soft Stop and (65h) TOFF_FALL Command
      10. 6.3.10 Power Good (PGOOD)
      11. 6.3.11 Set Switching Frequency
      12. 6.3.12 Frequency Synchronization
      13. 6.3.13 Loop Follower Detection
      14. 6.3.14 Current Sensing and Sharing
      15. 6.3.15 Telemetry
      16. 6.3.16 Overcurrent Protection
      17. 6.3.17 Overvoltage and Undervoltage Protection
      18. 6.3.18 Overtemperature Management
      19. 6.3.19 Fault Management
      20. 6.3.20 Back-Channel Communication
      21. 6.3.21 Switching Node (SW)
      22. 6.3.22 PMBus General Description
      23. 6.3.23 PMBus Address
      24. 6.3.24 PMBus Connections
    4. 6.4 Device Functional Modes
      1. 6.4.1 Programming Mode
      2. 6.4.2 Standalone, Loop Controller, and Loop Follower Mode Pin Connections
      3. 6.4.3 Continuous Conduction Mode
      4. 6.4.4 Operation With CNTL Signal (EN/UVLO)
      5. 6.4.5 Operation with (01h) OPERATION Control
      6. 6.4.6 Operation with CNTL and (01h) OPERATION Control
    5. 6.5 Programming
      1. 6.5.1 Supported PMBus Commands
      2. 6.5.2 Pin Strapping
        1. 6.5.2.1 Programming MSEL1
        2. 6.5.2.2 Programming MSEL2
        3. 6.5.2.3 Programming VSEL
        4. 6.5.2.4 Programming ADRSEL
        5. 6.5.2.5 Programming MSEL2 for a Loop Follower Device (GOSNS Tied to BP1V5)
        6. 6.5.2.6 Pin-Strapping Resistor Configuration
    6. 6.6 Register Maps
      1. 6.6.1  Conventions for Documenting Block Commands
      2. 6.6.2  (01h) OPERATION
      3. 6.6.3  (02h) ON_OFF_CONFIG
      4. 6.6.4  (03h) CLEAR_FAULTS
      5. 6.6.5  (04h) PHASE
      6. 6.6.6  (10h) WRITE_PROTECT
      7. 6.6.7  (15h) STORE_USER_ALL
      8. 6.6.8  (16h) RESTORE_USER_ALL
      9. 6.6.9  (19h) CAPABILITY
      10. 6.6.10 (1Bh) SMBALERT_MASK
      11. 6.6.11 (1Bh) SMBALERT_MASK_VOUT
      12. 6.6.12 (1Bh) SMBALERT_MASK_IOUT
      13. 6.6.13 (1Bh) SMBALERT_MASK_INPUT
      14. 6.6.14 (1Bh) SMBALERT_MASK_TEMPERATURE
      15. 6.6.15 (1Bh) SMBALERT_MASK_CML
      16. 6.6.16 (1Bh) SMBALERT_MASK_OTHER
      17. 6.6.17 (1Bh) SMBALERT_MASK_MFR
      18. 6.6.18 (20h) VOUT_MODE
      19. 6.6.19 (21h) VOUT_COMMAND
      20. 6.6.20 (22h) VOUT_TRIM
      21. 6.6.21 (24h) VOUT_MAX
      22. 6.6.22 (25h) VOUT_MARGIN_HIGH
      23. 6.6.23 (26h) VOUT_MARGIN_LOW
      24. 6.6.24 (27h) VOUT_TRANSITION_RATE
      25. 6.6.25 (29h) VOUT_SCALE_LOOP
      26. 6.6.26 (2Bh) VOUT_MIN
      27. 6.6.27 (33h) FREQUENCY_SWITCH
      28. 6.6.28 (35h) VIN_ON
      29. 6.6.29 (36h) VIN_OFF
      30. 6.6.30 (37h) INTERLEAVE
      31. 6.6.31 (38h) IOUT_CAL_GAIN
      32. 6.6.32 (39h) IOUT_CAL_OFFSET
      33. 6.6.33 (40h) VOUT_OV_FAULT_LIMIT
      34. 6.6.34 (41h) VOUT_OV_FAULT_RESPONSE
      35. 6.6.35 (42h) VOUT_OV_WARN_LIMIT
      36. 6.6.36 (43h) VOUT_UV_WARN_LIMIT
      37. 6.6.37 (44h) VOUT_UV_FAULT_LIMIT
      38. 6.6.38 (45h) VOUT_UV_FAULT_RESPONSE
      39. 6.6.39 (46h) IOUT_OC_FAULT_LIMIT
      40. 6.6.40 (47h) IOUT_OC_FAULT_RESPONSE
      41. 6.6.41 (4Ah) IOUT_OC_WARN_LIMIT
      42. 6.6.42 (4Fh) OT_FAULT_LIMIT
      43. 6.6.43 (50h) OT_FAULT_RESPONSE
      44. 6.6.44 (51h) OT_WARN_LIMIT
      45. 6.6.45 (55h) VIN_OV_FAULT_LIMIT
      46. 6.6.46 (56h) VIN_OV_FAULT_RESPONSE
      47. 6.6.47 (58h) VIN_UV_WARN_LIMIT
      48. 6.6.48 (60h) TON_DELAY
      49. 6.6.49 (61h) TON_RISE
      50. 6.6.50 (62h) TON_MAX_FAULT_LIMIT
      51. 6.6.51 (63h) TON_MAX_FAULT_RESPONSE
      52. 6.6.52 (64h) TOFF_DELAY
      53. 6.6.53 (65h) TOFF_FALL
      54. 6.6.54 (78h) STATUS_BYTE
      55. 6.6.55 (79h) STATUS_WORD
      56. 6.6.56 (7Ah) STATUS_VOUT
      57. 6.6.57 (7Bh) STATUS_IOUT
      58. 6.6.58 (7Ch) STATUS_INPUT
      59. 6.6.59 (7Dh) STATUS_TEMPERATURE
      60. 6.6.60 (7Eh) STATUS_CML
      61. 6.6.61 (7Fh) STATUS_OTHER
      62. 6.6.62 (80h) STATUS_MFR_SPECIFIC
      63. 6.6.63 (88h) READ_VIN
      64. 6.6.64 (8Bh) READ_VOUT
      65. 6.6.65 (8Ch) READ_IOUT
      66. 6.6.66 (8Dh) READ_TEMPERATURE_1
      67. 6.6.67 (98h) PMBUS_REVISION
      68. 6.6.68 (99h) MFR_ID
      69. 6.6.69 (9Ah) MFR_MODEL
      70. 6.6.70 (9Bh) MFR_REVISION
      71. 6.6.71 (9Eh) MFR_SERIAL
      72. 6.6.72 (ADh) IC_DEVICE_ID
      73. 6.6.73 (AEh) IC_DEVICE_REV
      74. 6.6.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
      75. 6.6.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
      76. 6.6.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
      77. 6.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
      78. 6.6.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
      79. 6.6.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
      80. 6.6.80 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
      81. 6.6.81 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
      82. 6.6.82 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
      83. 6.6.83 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
      84. 6.6.84 (EFh) MFR_SPECIFIC_31 (DEVICE_ADDRESS)
      85. 6.6.85 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
      86. 6.6.86 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
      87. 6.6.87 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
      88. 6.6.88 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  Switching Frequency
        3. 7.2.2.3  Output Voltage Setting (VSEL Pin)
        4. 7.2.2.4  Compensation Selection (MSEL1 Pin)
        5. 7.2.2.5  Output Capacitor Selection
          1. 7.2.2.5.1 Output Voltage Ripple
        6. 7.2.2.6  Input Capacitor Selection
        7. 7.2.2.7  Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        8. 7.2.2.8  Enable and UVLO
        9. 7.2.2.9  ADRSEL
        10. 7.2.2.10 BCX_CLK and BCX_DAT
      3. 7.2.3 Application Curves
    3. 7.3 Two-Phase Application
      1. 7.3.1 Design Requirements
      2. 7.3.2 Two-Phase Detailed Design Procedure
        1. 7.3.2.1  Switching Frequency
        2. 7.3.2.2  Output Voltage Setting (VSEL Pin)
        3. 7.3.2.3  Compensation Selection (MSEL1 Pin)
        4. 7.3.2.4  Output Capacitor Selection
        5. 7.3.2.5  Input Capacitor Selection
        6. 7.3.2.6  GOSNS/Loop Follower Pin of Loop Follower Devices
        7. 7.3.2.7  Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        8. 7.3.2.8  Enable, UVLO
        9. 7.3.2.9  VSHARE Pin
          1. 7.3.2.9.1 ADRSEL Pin
        10. 7.3.2.10 SYNC Pin
        11. 7.3.2.11 VOSNS Pin of Loop Follower Devices
        12. 7.3.2.12 Unused Pins of Loop Follower Devices
      3. 7.3.3 Application Curves
    4. 7.4 Four-Phase Application
    5. 7.5 Power Supply Recommendations
    6. 7.6 Layout
      1. 7.6.1 Layout Guidelines
      2. 7.6.2 Layout Example
        1. 7.6.2.1 Thermal Performance on the TI EVM
        2. 7.6.2.2 EMI
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
        1. 8.1.2.1 Texas Instruments Fusion Digital Power Designer
        2. 8.1.2.2 Custom Design With WEBENCH® Tools
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • MOW|59
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6.32 (39h) IOUT_CAL_OFFSET

CMD Address39h
Write Transaction:Write Word
Read Transaction:Read Word
Format:SLINEAR11, per CAPABILITY
Phased:Yes
NVM Backup:EEPROM
Updates:On-the-fly

IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT command. Each PHASE in a stack can apply an independent IOUT_CAL_OFFSET value. The effective IOUT_CAL_OFFSET value for a stack is equal to the sum of the IOUT_CAL_OFFSET values from all devices in the stack.

Figure 6-38 (39h) IOUT_CAL_OFFSET Register Map
15141312111098
RWRWRWRWRWRWRWRW
IOCOS_EXPIOCOS_MAN
76543210
RWRWRWRWRWRWRWRW
IOCOS_MAN
LEGEND: R/W = Read/Write; R = Read only
Table 6-49 Register Field Descriptions
BitFieldAccessResetDescription
15:11IOCOS_ EXPRW11100bLinear format, two’s complement exponent
10:0IOCOS_ MANRWNVMLinear format, two’s complement mantissa

Attempts to write (39h) IOUT_CAL_OFFSET to any value outside those specified as valid are considered invalid or unsupported data and cause the TPSM8D6C24 to respond by flagging the appropriate status bits and notifying the host according to the PMBus 1.3.1 Part II specification section 10.9.3.

Command Resolution and NVM Store or Restore Behavior

The (39h) IOUT_CAL_OFFSET command is implemented using the TPSM8D6C24 internal telemetry system. As a result, the value of this command can be programmed with very high resolution using the linear format. However, the TPSM8D6C24 only provides limited NVM-backed options for this command. Following a power-cycle or NVM Store and Restore operation, the value is restored to one of the supported values, according to the value present during the last NVM store operation. During operation, updates to this command with higher resolution are supported, and accepted as long as they fall between the minimum and maximum supported values given.

Phased Command Behavior

PHASE = 00h to 03h: Writes to (39h) IOUT_CAL_OFFSET modify the current sense offset for individual phases. Reads to (39h) IOUT_CAL_OFFSET return the configured current sense offset for individual phases.

PHASE = FFh: Writes to (39h) IOUT_CAL_OFFSET modify the total current sense offset for all individual phases. Individual phases are assigned an IOUT_CAL_OFFSET value equal to the written value divided by the number of phases. Reads to (39h) IOUT_CAL_OFFSET return the configured current sense offset for PHASE = 00h times the number of phases.