SLUSEJ1A December 2021 – November 2023 TPSM8D6C24
PRODUCTION DATA
CMD Address | 33h |
Write Transaction: | Write Word |
Read Transaction: | Read Word |
Format: | SLINEAR11, per CAPABILITY |
Phased: | No |
Updates: | Conversion Disable: on-the-fly. Conversion Enable: hardware update blocked. To update hardware after write while enabled, store to NVM with STORE_USER_ALL and RESTORE_USER_ALL or cycle AVIN below UVLO. |
NVM Backup: | EEPROM or Pin Detection |
FREQUENCY_SWITCH sets the switching frequency of the active channel in kHz.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RW | RW | RW | RW | RW | RW | RW | RW |
FSW_EXP | FSW_MAN | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RW | RW | RW | RW | RW | RW | RW | RW |
FSW_MAN |
LEGEND: R/W = Read/Write; R = Read only |
Bit | Field | Access | Reset | Description |
---|---|---|---|---|
15:11 | FSW_ EXP | RW | NVM | Linear format two’s complement exponent On reset, FSW_EXP is auto-generated based on the switching frequency stored in NVM. |
10:0 | FSW_ MAN | RW | NVM | Linear format two’s complement mantissa. Refer to Table 6-43. |
FREQUENCY_SWITCH (Decoded) | Effective Switching Frequency (kHz) |
---|---|
Less than 250 kHz | 225 |
251 ≤ FSW < 300 kHz | 275 |
301 ≤ FSW < 350 kHz | 325 |
351 ≤ FSW < 410 kHz | 375 |
411 ≤ FSW < 500 kHz | 450 |
501 ≤ FSW < 600 kHz | 550 |
601 ≤ FSW < 700 kHz | 650 |
701 ≤ FSW < 820 kHz | 750 |
821 ≤ FSW < 1000 kHz | 900 |
1001 ≤ FSW < 1200 kHz | 1100 |
1201 ≤ FSW < 1400 kHz | 1300 |
1401 ≤ FSW < 1650 kHz | 1500 |
FREQUENCY_SWITCH values greater than 1100 kHz can require higher VDD5 current than can be provided by the internal AVIN to VDD5 linear regulator. Programming FREQUENCY_SWITCH to a value greater than 1100 kHz without an external source to VDD5 can result in repeated start-up and shutdown attempt. FRQUENCY_SWITCH values greater than 1100 kHz are not recommended for stacked multi-phase operation.