SBOS972C october   2021  – august 2023 TRF1208

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: TRF1208
    6. 6.6 Electrical Characteristics: TRF1208B
    7. 6.7 Typical Characteristics: TRF1208
    8. 6.8 Typical Characteristics: TRF1208B
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully-Differential Amplifier
      2. 7.3.2 Single Supply Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Driving a High-Speed ADC
      2. 8.1.2 Calculating Output Voltage Swing
      3. 8.1.3 Thermal Considerations
    2. 8.2 Typical Applications
      1. 8.2.1 TRF1208 in Receive Chain
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
      2. 8.2.2 TRF1208 in a Transmit Chain
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics: TRF1208

at TA = 25°C, VDD = 3.3 V, 50-Ω single-ended input, and 100-Ω differential output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal 3-dB bandwidth VO = 0.1 VPP 11 GHz
LSBW Large-signal 3-dB bandwidth VO = 1 VPP 11 GHz
1-dB BW Bandwidth for 1-dB flatness 8 GHz
S21 Power gain f = 2 GHz 16 dB
S11 Input return loss f = 10 MHz to 8 GHz –10 dB
S12 Reverse isolation f = 2 GHz –35 dB
ImbGAIN Gain imbalance f = 10 MHz to 8 GHz ± 0.3 dB
ImbPHASE Phase imbalance f = 10 MHz to 8 GHz ± 3 °
CMRR Common-mode rejection ratio(1) f = 2 GHz –45 dB
HD2 Second-order harmonic distortion f = 0.5 GHz, PO = +3 dBm –70 dBc
f = 2 GHz, PO = +3 dBm –65
f = 6 GHz, PO = +3 dBm –52
f = 8 GHz, PO = +3 dBm –45
HD3 Third-order harmonic distortion f = 0.5 GHz, PO = +3 dBm –68 dBc
f = 2 GHz, PO = +3 dBm –63
f = 6 GHz, PO = +3 dBm –56
f = 8 GHz, PO = +3 dBm –63
IMD2 Second-order intermodulation distortion f = 0.5 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –73 dBc
f = 2 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –69
f = 6 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –56
f = 8 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –45
IMD3 Third-order intermodulation distortion f = 0.5 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –75 dBc
f = 2 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –84
f = 6 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –72
f = 8 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 –51
OP1dB Output 1-dB compression point f = 0.5 GHz 11 dBm
f = 2 GHz 15
f = 6 GHz 12.5
f = 8 GHz 7.5
OIP2 Output second-order intercept point f = 0.5 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 68 dBm
f = 2 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 63
f = 6 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 55
f = 8 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 42
OIP3 Output third-order intercept point f = 0.5 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 34 dBm
f = 2 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 37
f = 4 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 34
f = 6 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 30
f = 8 GHz, PO = –4 dBm per tone
(10-MHz spacing)		 21
NF Noise figure f = 0.5 GHz 6.5 dB
f = 2 GHz 6.8
f = 6 GHz 7.2
f = 8 GHz 7
IMPEDANCE
ZO-DIFF Differential output impedance f = dc (internal to the device) 3 Ω
ZIN Single-ended input impedance INM pin terminated with 50 Ω 50 Ω
TRANSIENT
VOMAX Maximum output voltage (differential) 2 VPP
VOSAT Saturated output voltage level (differential) f = 2 GHz 3.9 VPP
tREC Overdrive recovery time Using a –0.5-VP input pulse of 2-ns duration 0.2 ns
POWER SUPPLY
IQA Active current Current on VDD pin, PD = 0 138 mA
IQPD Power-down quiescent current Current on VDD pin, PD = 1 7 mA
ENABLE
VPDHIGH PD pin logic high 1.45 V
VPDLOW PD pin logic low 0.8 V
IPDBIAS PD bias current (current on PD pin) PD = high (1.8-V logic) 50 100 µA
PD = high (3.3-V logic) 200 250
CPD PD pin capacitance 2 pF
tON Turn-on time 50% VPD to 90% RF 200 ns
tOFF Turn-off time 50% VPD to 10% RF 50 ns
(1) Calculated using the formula (S21-S31)/(S21+S31). Port-1: INP, Port-2: OUTP, Port-3: OUTM.