SLWS230E September 2011 – December 2015 TRF3765
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage (2) | All VCC pins except VCC_TK | –0.3 | 3.6 | V |
VCC_TK | –0.3 | 5.5 | ||
Digital I/O voltage | –0.3 | VI + 0.5 | V | |
Operating virtual junction temperature, TJ | –40 | 150 | °C | |
Operating ambient temperature, TA | –40 | 85 | °C | |
Storage temperature, Tstg | –40 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±1000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | Power-supply voltage | 3 | 3.3 | 3.6 | V |
VCC_TK | 3.3-V to 5.5-V power-supply voltage | 3 | 3.3 | 5.5 | V |
TA | Operating ambient temperature | –40 | 85 | °C | |
TJ | Operating virtual junction temperature | –40 | 150 | °C |
THERMAL METRIC(1) | TRF3765 | UNIT | |
---|---|---|---|
RHB (VQFN) | |||
32 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 31.6 | °C/W |
RθJCtop | Junction-to-case (top) thermal resistance | 21.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 5.6 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 5.5 | °C/W |
RθJCbot | Junction-to-case (bottom) thermal resistance | 1.1 | °C/W |
PARAMETERS | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DC PARAMETERS | |||||||
ICC | Total supply current | Internal VCO, 1 output buffer on, divide-by-1 | 115 | mA | |||
Internal VCO, 4 output buffers on, divide-by-1 | 190 | ||||||
Internal VCO, 1 output buffer on, divide-by-8 | 120 | ||||||
Internal VCO, 4 output buffers on, divide-by-8 | 182 | ||||||
External VCO mode, 1 output buffer on, divide-by-1 | 89 | ||||||
DIGITAL INTERFACE | |||||||
VIH | High-level input voltage | 2 | 3.3 | V | |||
VIL | Low-level input voltage | 0 | 0.8 | ||||
VOH | High-level output voltage | Referenced to VCC_DIG | 0.8 × VCC | ||||
VOL | Low-level output voltage | Referenced to VCC_DIG | 0.2 × VCC | ||||
REFERENCE OSCILLATOR PARAMETERS | |||||||
fREF | Reference frequency | 0.5(6) | 350(6) | MHz | |||
Reference input sensitivity | 0.2 | 3.3 | VPP | ||||
Reference input impedance | Parallel capacitance, 10 MHz | 2 | pF | ||||
Parallel resistance, 10 MHz | 2500 | Ω | |||||
PLL | |||||||
fPFD | PFD frequency | 0.5 | 65(1) | MHz | |||
ICP_OUT | Charge pump current | 4WI programmable; ICP[4..0] = 00000(2) | 1.94 | mA | |||
In-band normalized phase noise floor | Integer mode | –221 | dBc/Hz | ||||
INTERNAL VCO | |||||||
fVCO | VCO frequency range | Divide-by-1 | 2400 | 4800 | MHz | ||
KV | VCO gain | VCP = 1 V | –65 | MHz/V | |||
VCO free-running phase noise, fVCO = 2650 MHz |
VCC_TK = 3.3 V | At 10 kHz | –82 | dBc/Hz | |||
At 100 kHz | –110 | ||||||
At 1 MHz | –130 | ||||||
At 10 MHz | –149 | ||||||
At 40 MHz | –155 | ||||||
VCC_TK = 5 V | At 10 kHz | –89 | dBc/Hz | ||||
At 100 kHz | –113 | ||||||
At 1 MHz | –133 | ||||||
At 10 MHz | –151 | ||||||
At 40 MHz | –156 | ||||||
CLOSED-LOOP PLL/VCO | |||||||
Integrated RMS jitter(3) | Fractional mode, fOUT = 2.6 GHz, fPFD = 30.72 MHz(4) | 0.36 | ps | ||||
Integer mode, fOUT = 2.6 GHz, fPFD = 1.6 MHz | 0.52 | ||||||
RF OUTPUT/INPUT | |||||||
fOUT | Output frequency range | Divide-by-1 | 2400 | 4800 | MHz | ||
Divide-by-2 | 1200 | 2400 | |||||
Divide-by-4 | 600 | 1200 | |||||
Divide-by-8 | 300 | 600 | |||||
PLO | Output power(5) | Differential, divide-by-1, one output buffer on, maximum BUFOUT_BIAS | 6.5 | dBm | |||
External VCO input maximum frequency | 20-dB gain loss, VCO pass-through, no PLL | 9000 | MHz | ||||
External VCO input minimum frequency | 20-dB gain loss, VCO pass-through, no PLL, divide-by-1 | 15 | MHz | ||||
External VCO input level | 0 | dBm |
MIN | MAX | UNIT | ||
---|---|---|---|---|
th | Hold time, data to clock | 20 | ns | |
tsu1 | Setup time, data to clock | 20 | ns | |
t(CH) | Clock low duration | 20 | ns | |
t(CL) | Clock high duration | 20 | ns | |
tsu2 | Setup time, clock to enable | 20 | ns | |
t(CLK) | Clock period | 50 | ns | |
tw | Enable time | 50 | ns | |
tsu3 | Setup time, latch to data | 70 | ns |
MIN | MAX | UNIT | ||
---|---|---|---|---|
th | Hold time, data to clock | 20 | ns | |
tsu1 | Setup time, data to clock | 20 | ns | |
t(CH) | Clock low duration | 20 | ns | |
t(CL) | Clock high duration | 20 | ns | |
tsu2 | Setup time, clock to enable | 20 | ns | |
tsu3 | Setup time, enable to Readback clock | 20 | ns | |
td | Delay time, clock to Readback data output | 10 | ns | |
tw(1) | Enable time | 50 | ns | |
t(CLK) | Clock period | 50 | ns |
GRAPH NAME | FIGURE NO. | |
Open-Loop Phase Noise | vs Temperature(1) | Figure 3, Figure 4, Figure 5, Figure 6 |
Open-Loop Phase Noise | vs Voltage(1) | Figure 7, Figure 8, Figure 9, Figure 10 |
Open-Loop Phase Noise | vs Temperature(1)(2) | Figure 11, Figure 12, Figure 13, Figure 14 |
Open-Loop Phase Noise | vs Voltage(1)(2) | Figure 15, Figure 16, Figure 17, Figure 18 |
Closed-Loop Phase Noise | vs Temperature(3) | Figure 19, Figure 20, Figure 21, Figure 22, Figure 23, Figure 24, Figure 25 |
Closed-Loop Phase Noise | vs Temperature(2)(3) | Figure 26, Figure 27, Figure 28, Figure 29, Figure 30, Figure 31, Figure 32 |
Closed-Loop Phase Noise | vs Divide Ratio(3) | Figure 33 |
Closed-Loop Phase Noise | vs Divide Ratio(2)(3) | Figure 34 |
Closed-Loop Phase Noise | vs Temperature(4) | Figure 35, Figure 36, Figure 37, Figure 38, Figure 39, Figure 40, Figure 41 |
Closed-Loop Phase Noise | vs Temperature(2)(4) | Figure 42, Figure 43, Figure 44, Figure 45, Figure 46, Figure 47, Figure 48 |
Closed-Loop Phase Noise | vs Divide Ratio(4) | Figure 49 |
Closed-Loop Phase Noise | vs Divide Ratio(2)(4) | Figure 50 |
PFD Spurs | vs Temperature(4) | Figure 51 |
Multiples of PFD Spurs(4) | Figure 52, Figure 53, Figure 54 | |
Multiples of PFD Spurs(4)(5) | Figure 55 | |
Fractional Spurs | vs LO Divider(3) | Figure 56 |
Fractional Spurs | vs RF Divider and Prescaler(3) | Figure 57 |
Fractional Spurs | vs Temperature(3) | Figure 58 |
Multiples of PFD Spurs(3) | Figure 59 | |
LO Harmonics(4) | Figure 60 | |
Output Power with Multiple Buffers(4) | Figure 61, Figure 62 | |
Output Power | vs Output Port(4) | Figure 63 |
Output Power | vs Buffer Bias(4) | Figure 64 |
VCO Gain (Kv) | vs Frequency | Figure 65 |