SLOS732G June   2011  – March 2020 TRF7960A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Application Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Functional Block Diagram
    2. 6.2  Power Supplies
    3. 6.3  Supply Arrangements
    4. 6.4  Supply Regulator Settings
    5. 6.5  Power Modes
    6. 6.6  Receiver – Analog Section
      1. 6.6.1 Main and Auxiliary Receiver
      2. 6.6.2 Receiver Gain and Filter Stages
    7. 6.7  Receiver – Digital Section
      1. 6.7.1 Received Signal Strength Indicator (RSSI)
        1. 6.7.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.7.1.2 External RSSI
    8. 6.8  Oscillator Section
    9. 6.9  Transmitter - Analog Section
    10. 6.10 Transmitter - Digital Section
    11. 6.11 Transmitter – External Power Amplifier or Subcarrier Detector
    12. 6.12 Communication Interface
      1. 6.12.1 General Introduction
      2. 6.12.2 FIFO Operation
      3. 6.12.3 Parallel Interface Mode
      4. 6.12.4 Reception of Air Interface Data
      5. 6.12.5 Data Transmission to MCU
      6. 6.12.6 Serial Interface Communication (SPI)
        1. 6.12.6.1 Serial Interface Mode Without Slave Select (SS)
        2. 6.12.6.2 Serial Interface Mode With Slave Select (SS)
      7. 6.12.7 Direct Mode
    13. 6.13 Direct Commands from MCU to Reader
      1. 6.13.1  Command Codes
      2. 6.13.2  Reset FIFO (0x0F)
      3. 6.13.3  Transmission With CRC (0x11)
      4. 6.13.4  Transmission Without CRC (0x10)
      5. 6.13.5  Delayed Transmission With CRC (0x13)
      6. 6.13.6  Delayed Transmission Without CRC (0x12)
      7. 6.13.7  Transmit Next Time Slot (0x14)
      8. 6.13.8  Block Receiver (0x16)
      9. 6.13.9  Enable Receiver (0x17)
      10. 6.13.10 Test Internal RF (RSSI at RX Input With TX On) (0x18)
      11. 6.13.11 Test External RF (RSSI at RX Input With TX Off) (0x19)
      12. 6.13.12 Register Preset
    14. 6.14 Register Description
      1. 6.14.1 Register Overview
        1. 6.14.1.1 Main Configuration Registers
          1. 6.14.1.1.1 Chip Status Control Register (0x00)
          2. 6.14.1.1.2 ISO Control Register (0x01)
        2. 6.14.1.2 Protocol Subsetting Registers
          1. 6.14.1.2.1  ISO14443B TX Options Register (0x02)
          2. 6.14.1.2.2  ISO14443A High-Bit-Rate and Parity Options Register (0x03)
          3. 6.14.1.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.14.1.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.14.1.2.5  TX Pulse Length Control Register (0x06)
          6. 6.14.1.2.6  RX No Response Wait Time Register (0x07)
          7. 6.14.1.2.7  RX Wait Time Register (0x08)
          8. 6.14.1.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.14.1.2.9  RX Special Setting Register (0x0A)
          10. 6.14.1.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.14.1.3 Status Registers
          1. 6.14.1.3.1 IRQ Status Register (0x0C)
          2. 6.14.1.3.2 Collision Position and Interrupt Mask Registers (0x0D and 0x0E)
          3. 6.14.1.3.3 RSSI Levels and Oscillator Status Register (0x0F)
        4. 6.14.1.4 Test Registers
          1. 6.14.1.4.1 Test Register (0x1A)
          2. 6.14.1.4.2 Test Register (0x1B)
        5. 6.14.1.5 FIFO Control Registers
          1. 6.14.1.5.1 FIFO Status Register (0x1C)
          2. 6.14.1.5.2 TX Length Byte1 Register (0x1D) and TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7960A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 System Design
      1. 7.2.1 Layout Considerations
      2. 7.2.2 Impedance Matching TX_Out (Pin 5) to 50 Ω
      3. 7.2.3 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1 Signal Descriptions

TERMINAL TYPE (1) DESCRIPTION
NO. NAME
1 VDD_A OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
2 VIN SUP External supply input to chip (2.7 V to 5.5 V)
3 VDD_RF OUT Internal regulated supply (2.7 V to 5 V); normally connected to VDD_PA (pin 4)
4 VDD_PA INP Supply for PA; normally connected externally to VDD_RF (pin 3)
5 TX_OUT OUT RF output (selectable output power: 100 mW or 200 mW, with VDD = 5 V)
6 VSS_PA SUP Negative supply for PA; normally connected to circuit ground
7 VSS_RX SUP Negative supply for receive inputs; normally connected to circuit ground
8 RX_IN1 INP Main receive input
9 RX_IN2 INP Auxiliary receive input
10 VSS SUP Chip substrate ground
11 BAND_GAP OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference
12 ASK/OOK BID Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 and 1.

It can be configured as an output to provide the received analog signal output.
13 IRQ OUT Interrupt request
14 MOD INP External data modulation input for direct mode 0 or 1
OUT Subcarrier digital data output (see register 0x1A and 0x1B definitions)
15 VSS_A SUP Negative supply for internal analog circuits. Connected to GND.
16 VDD_I/O INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded.
17 I/O_0 BID I/O pin for parallel communication
18 I/O_1 BID I/O pin for parallel communication
19 I/O_2 BID I/O pin for parallel communication
20 I/O_3 BID I/O pin for parallel communication
21 I/O_4 BID I/O pin for parallel communication

Slave select signal in SPI mode
22 I/O_5 BID I/O pin for parallel communication

Data clock output in direct mode 1
23 I/O_6 BID I/O pin for parallel communication

MISO for serial communication (SPI)

Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0
24 I/O_7 BID I/O pin for parallel communication.

MOSI for serial communication (SPI)
25 EN2 INP Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU).
26 DATA_CLK INP Data clock input for MCU communication (parallel and serial)
27 SYS_CLK OUT If EN = 1 (EN2 = don't care) the system clock for the MCU is configured with register 0x09 (off, 3.39 MHz, 6.78 MHz, or 13.56 MHz).

If EN = 0 and EN2 = 1, the system clock is set to 60 kHz.
28 EN INP Chip enable input (if EN = 0, then the chip is in sleep or power-down mode)
29 VSS_D SUP Negative supply for internal digital circuits
30 OSC_OUT OUT Crystal or oscillator output
31 OSC_IN INP Crystal or oscillator input
32 VDD_X OUT Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an MCU)
PAD PAD SUP Chip substrate ground
(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output