6.10.5.1 Serial Interface Mode With Slave Select (SS)

The serial interface is in reset while the Slave Select signal is high. Serial data in (MOSI) changes on the rising edge, and is validated in the reader on the falling edge, as shown in Figure 6-19. Communication is terminated when the Slave Select signal goes high.

All words must be 8 bits long with the MSB transmitted first.

Figure 6-19 SPI With Slave Select Timing Diagram

The read command is sent out on the MOSI pin, MSB first, in the first eight clock cycles. MOSI data changes on the rising edge, and is validated in the reader on the falling edge, as shown in Figure 6-19. During the write cycle, the serial data out (MISO) is not valid. After the last read command bit (B0) is validated at the eighth falling edge of SCLK, valid data can be read on the MISO pin at the falling edge of SCLK. It takes eight clock edges to read out the full byte (MSB first). See Section 5.4 for electrical specifications related to Figure 6-19.

Figure 6-20 and Figure 6-21 show the continuous read operation.

Figure 6-20 Continuous Read Operation Using SPI With Slave Select

Figure 6-21 Continuous Read of Registers 0x00 to 0x05 Using SPI With SS

Figure 6-22 shows an example of performing a single slot inventory command. Reader registers (in this example) are configured for 5 VDC in and default operation.

Figure 6-22 Inventory Command Sent From MCU to TRF7964A

The TRF7964A takes these bytes from the MCU and then send out Request Flags, Inventory Command, and Mask over the air to the ISO/IEC 15693 transponder. After these three bytes have been transmitted, an interrupt occurs to indicate back to the reader that the transmission has been completed. In the example in Figure 6-23, this IRQ occurs approximately 1.6 ms after the SS line goes high after the Inventory command is sent out.

Figure 6-23 IRQ After Inventory Command

The IRQ status register read (0x6C) yields 0x80, which indicates that TX is indeed complete. This is followed by a dummy clock. Then, if a tag is in the field and no error is detected by the reader, a second interrupt is expected and occurs (in this example) approximately 4 ms after first IRQ is read and cleared.

In the continuation of the example (see Figure 6-24), the IRQ Status Register is read using method previously recommended, followed by a single read of the FIFO Status register, which indicates that there are 10 bytes to be read out.

Figure 6-24 Read IRQ Status Register After Inventory Command

This is then followed by a continuous read of the FIFO (see Figure 6-25). The first byte is (and should be) 0x00 for no error. The next byte is the DSFID (usually shipped by manufacturer as 0x00), then the UID, shown here up to the next most significant byte, the MFG code [shown as 0x07 (TI silicon)].

Figure 6-25 Continuous Read of FIFO After Inventory Command

TI recommends resetting the FIFO after receiving data. Additionally, the RSSI value of the tag can be read out at this point. In the example in Figure 6-26, the transponder is very close to the antenna, so value of 0x7F is recovered.

Figure 6-26 Reset FIFO and Read RSSI