SLOS743M August   2011  – March 2020 TRF7970A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Characteristics
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Electrical Characteristics
    5. 5.5 Thermal Resistance Characteristics
    6. 5.6 Switching Characteristics
  6. 6Detailed Description
    1. 6.1  Overview
      1. 6.1.1 RFID and NFC Operation – Reader and Writer
      2. 6.1.2 NFC Device Operation – Initiator
      3. 6.1.3 NFC Device Operation – Target
        1. 6.1.3.1 Active Target
        2. 6.1.3.2 Passive Target
        3. 6.1.3.3 Card Emulation
    2. 6.2  System Block Diagram
    3. 6.3  Power Supplies
      1. 6.3.1 Supply Arrangements
      2. 6.3.2 Supply Regulator Settings
      3. 6.3.3 Power Modes
    4. 6.4  Receiver – Analog Section
      1. 6.4.1 Main and Auxiliary Receivers
      2. 6.4.2 Receiver Gain and Filter Stages
    5. 6.5  Receiver – Digital Section
      1. 6.5.1 Received Signal Strength Indicator (RSSI)
        1. 6.5.1.1 Internal RSSI – Main and Auxiliary Receivers
        2. 6.5.1.2 External RSSI
    6. 6.6  Oscillator Section
    7. 6.7  Transmitter – Analog Section
    8. 6.8  Transmitter – Digital Section
    9. 6.9  Transmitter – External Power Amplifier and Subcarrier Detector
    10. 6.10 TRF7970A IC Communication Interface
      1. 6.10.1 General Introduction
        1. 6.10.1.1 Continuous Address Mode
        2. 6.10.1.2 Noncontinuous Address Mode (Single Address Mode)
        3. 6.10.1.3 Direct Command Mode
        4. 6.10.1.4 FIFO Operation
      2. 6.10.2 Parallel Interface Mode
      3. 6.10.3 Reception of Air Interface Data
      4. 6.10.4 Data Transmission From MCU to TRF7970A
      5. 6.10.5 Serial Interface Communication (SPI)
        1. 6.10.5.1 Serial Interface Mode With Slave Select (SS)
      6. 6.10.6 Direct Mode
    11. 6.11 TRF7970A Initialization
    12. 6.12 Special Direct Mode for Improved MIFARE Compatibility
    13. 6.13 NFC Modes
      1. 6.13.1 Target
      2. 6.13.2 Initiator
    14. 6.14 Direct Commands from MCU to Reader
      1. 6.14.1 Command Codes
        1. 6.14.1.1  Idle (0x00)
        2. 6.14.1.2  Software Initialization (0x03)
        3. 6.14.1.3  Initial RF Collision Avoidance (0x04)
        4. 6.14.1.4  Response RF Collision Avoidance (0x05)
        5. 6.14.1.5  Response RF Collision Avoidance (0x06, n = 0)
        6. 6.14.1.6  Reset FIFO (0x0F)
        7. 6.14.1.7  Transmission With CRC (0x11)
        8. 6.14.1.8  Transmission Without CRC (0x10)
        9. 6.14.1.9  Delayed Transmission With CRC (0x13)
        10. 6.14.1.10 Delayed Transmission Without CRC (0x12)
        11. 6.14.1.11 Transmit Next Time Slot (0x14)
        12. 6.14.1.12 Block Receiver (0x16)
        13. 6.14.1.13 Enable Receiver (0x17)
        14. 6.14.1.14 Test Internal RF (RSSI at RX Input With TX ON) (0x18)
        15. 6.14.1.15 Test External RF (RSSI at RX Input with TX OFF) (0x19)
    15. 6.15 Register Description
      1. 6.15.1 Register Preset
      2. 6.15.2 Register Overview
      3. 6.15.3 Detailed Register Description
        1. 6.15.3.1 Main Configuration Registers
          1. 6.15.3.1.1 Chip Status Control Register (0x00)
          2. 6.15.3.1.2 ISO Control Register (0x01)
        2. 6.15.3.2 Control Registers – Sublevel Configuration Registers
          1. 6.15.3.2.1  ISO/IEC 14443 TX Options Register (0x02)
          2. 6.15.3.2.2  ISO/IEC 14443 High-Bit-Rate and Parity Options Register (0x03)
          3. 6.15.3.2.3  TX Timer High Byte Control Register (0x04)
          4. 6.15.3.2.4  TX Timer Low Byte Control Register (0x05)
          5. 6.15.3.2.5  TX Pulse Length Control Register (0x06)
          6. 6.15.3.2.6  RX No Response Wait Time Register (0x07)
          7. 6.15.3.2.7  RX Wait Time Register (0x08)
          8. 6.15.3.2.8  Modulator and SYS_CLK Control Register (0x09)
          9. 6.15.3.2.9  RX Special Setting Register (0x0A)
          10. 6.15.3.2.10 Regulator and I/O Control Register (0x0B)
        3. 6.15.3.3 Status Registers
          1. 6.15.3.3.1  IRQ Status Register (0x0C)
          2. 6.15.3.3.2  Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
          3. 6.15.3.3.3  RSSI Levels and Oscillator Status Register (0x0F)
          4. 6.15.3.3.4  Special Functions Register (0x10)
          5. 6.15.3.3.5  Special Functions Register (0x11)
          6. 6.15.3.3.6  Adjustable FIFO IRQ Levels Register (0x14)
          7. 6.15.3.3.7  NFC Low Field Level Register (0x16)
          8. 6.15.3.3.8  NFCID1 Number Register (0x17)
          9. 6.15.3.3.9  NFC Target Detection Level Register (0x18)
          10. 6.15.3.3.10 NFC Target Protocol Register (0x19)
        4. 6.15.3.4 Test Registers
          1. 6.15.3.4.1 Test Register (0x1A)
          2. 6.15.3.4.2 Test Register (0x1B)
        5. 6.15.3.5 FIFO Control Registers
          1. 6.15.3.5.1 FIFO Status Register (0x1C)
          2. 6.15.3.5.2 TX Length Byte1 Register (0x1D), TX Length Byte2 Register (0x1E)
  7. 7Applications, Implementation, and Layout
    1. 7.1 TRF7970A Reader System Using SPI With SS Mode
      1. 7.1.1 General Application Considerations
      2. 7.1.2 Schematic
    2. 7.2 Layout Considerations
    3. 7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω
    4. 7.4 Reader Antenna Design Guidelines
  8. 8Device and Documentation Support
    1. 8.1 Getting Started and Next Steps
    2. 8.2 Device Nomenclature
    3. 8.3 Tools and Software
    4. 8.4 Documentation Support
    5. 8.5 Support Resources
    6. 8.6 Trademarks
    7. 8.7 Electrostatic Discharge Caution
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1 Terminal Functions

TERMINAL TYPE (1) DESCRIPTION
NAME NO.
VDD_A 1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry
VIN 2 SUP External supply input to chip (2.7 V to 5.5 V)
VDD_RF 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4)
VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3)
TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD = 5 V)
VSS_PA 6 SUP Negative supply for PA; normally connected to circuit ground
VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground
RX_IN1 8 INP Main RX input
RX_IN2 9 INP Auxiliary RX input
VSS 10 SUP Chip substrate ground
BAND_GAP 11 OUT Bandgap voltage (VBG = 1.6 V); internal analog voltage reference
ASK/OOK 12 BID Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 or 1.
Can be configured as an output to provide the received analog signal output.
IRQ 13 OUT Interrupt request
MOD 14 INP External data modulation input for direct mode 0 or 1
OUT Subcarrier digital data output (see registers 0x1A and 0x1B)
VSS_A 15 SUP Negative supply for internal analog circuits; connected to GND
VDD_I/O 16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded.
I/O_0 17 BID I/O pin for parallel communication
I/O_1 18 BID I/O pin for parallel communication
I/O_2 19 BID I/O pin for parallel communication
TX enable (in special direct mode)
I/O_3 20 BID I/O pin for parallel communication
TX data (in special direct mode)
I/O_4 21 BID I/O pin for parallel communication
Slave select signal in SPI mode
I/O_5 22 BID I/O pin for parallel communication
Data clock output in direct mode 1 and special direct mode
I/O_6 23 BID I/O pin for parallel communication
MISO for serial communication (SPI)
Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0
I/O_7 24 BID I/O pin for parallel communication.
MOSI for serial communication (SPI)
EN2 25 INP Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU).
DATA_CLK 26 INP Data clock input for MCU communication (parallel and serial)
SYS_CLK 27 OUT

If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal that is used, options are as follows (see register 0x09):

13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz

27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz
If EN = 0 and EN2 = 1, then system clock is set to 60 kHz
EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode).
VSS_D 29 SUP Negative supply for internal digital circuits
OSC_OUT 30 OUT Crystal or oscillator output
OSC_IN 31 INP Crystal or oscillator input
OUT Crystal oscillator output
VDD_X 32 OUT Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an MCU)
Thermal Pad PAD SUP Chip substrate ground
(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output