SLLS810A July 2007 – July 2024 TRS208
PRODUCTION DATA
The HBM of ESD testing is shown in Figure 8-1, while Figure 8-2 shows the current waveform that is generated during a discharge into a low impedance. The model consists of a 100pF capacitor, charged to the ESD voltage of concern and subsequently discharged into the DUT through a 1.5kΩ resistor.