SCDS358B November   2014  – February 2015 TS3A227E

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 I2C Interface Timing Characteristics
    7. 7.7 Timing Diagrams
      1. 7.7.1 Removal
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Accessory Configuration Detection
      2. 9.3.2 Optional Manual I2C Control
      3. 9.3.3 Adjustable De-bounce Timings
      4. 9.3.4 Key Press Detection
      5. 9.3.5 Click Pop Noise Reduction
      6. 9.3.6 Power off Noise Removal
      7. 9.3.7 Sleep Mode
      8. 9.3.8 Codec Sense Line
      9. 9.3.9 FM Support
    4. 9.4 Device Functional Modes
      1. 9.4.1 Sleep Mode
      2. 9.4.2 Manual Switch Control
      3. 9.4.3 Manual Switch Control Use Cases
      4. 9.4.4 FM Support Mode
    5. 9.5 Register Maps
    6. 9.6 Register Field Descriptions
      1. 9.6.1  Device ID Register Field Descriptions (Address 00h)
      2. 9.6.2  Interrupt Register Field Descriptions (Address 01h)
      3. 9.6.3  Key Press Interrupt Register Field Descriptions (Address 02h)
      4. 9.6.4  Interrupt Disable Register Field Descriptions (Address 03h)
      5. 9.6.5  Device Settings Field Descriptions (Address 04h)
      6. 9.6.6  Key Press Settings 1 Field Descriptions (Address 05h)
      7. 9.6.7  Key Press Settings 2 Field Descriptions (Address 06h)
      8. 9.6.8  Switch Control 1 Field Descriptions (Address 07h)
      9. 9.6.9  Switch Control 2 Field Descriptions (Address 08h)
      10. 9.6.10 Switch Status 1 Field Descriptions (Address 09h)
      11. 9.6.11 Switch Status 2 Field Descriptions (Address 0Ah)
      12. 9.6.12 Detection Results Field Descriptions (Address 0Bh)
      13. 9.6.13 ADC Output Field Descriptions (Address 0Ch)
      14. 9.6.14 Threshold 1 Field Descriptions (Address 0Dh)
      15. 9.6.15 Threshold 2 Field Descriptions (Address 0Eh)
      16. 9.6.16 Threshold 3 Field Descriptions (Address 0Fh)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Standard I2C Interface Details
        2. 10.2.1.2 Write Operations
        3. 10.2.1.3 Read Operations
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Accessory Insertion
        2. 10.2.2.2 Audio Jack Selection
        3. 10.2.2.3 Switch Status
          1. 10.2.2.3.1 Switch Status Diagrams
        4. 10.2.2.4 Key Press Detection
          1. 10.2.2.4.1 Key Press Thresholds
          2. 10.2.2.4.2 System Requirements
          3. 10.2.2.4.3 Key Press Grey Zones
          4. 10.2.2.4.4 Behavior
          5. 10.2.2.4.5 Single Key Press Timing
          6. 10.2.2.4.6 Multiple Key Press Timing
          7. 10.2.2.4.7 Raw Data Key Press Detection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example (QFN)
    3. 12.3 Layout Example (DSBGA)
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

10.1 Application Information

Figure 19 shows how a standard application schematic for the TS3A227E. The DSBGA package pin connections will be the same except for the lack of thermal pad. The following sections discuss how the TS3A227E works with different headsets and how the key press detection operates.

10.2 Typical Application

exmpl_sch_scds358.gifFigure 19. Typical Application Schematic

Table 17. Component List

COMPONENT VALUE NOTES
R1 4.7 kΩ Pullup resistor must be sized to not exceed max IOL specification for INT pin
R2 4.7 kΩ Pullup resistor must be sized to not exceed max IOL specification for INT pin
R3 4.7 kΩ Pullup resistor must be sized to not exceed max IOL specification for INT pin
R4 4.7 kΩ Pullup resistor must be sized to not exceed max IOL specification for INT pin
R5 10 kΩ Pulldown resistor for high to low transition on DET_TRIGGER
R6 2.2 kΩ ±1% MICBIAS pullup resistor must be ±1% for Key Press Detection to function properly
C1 10 µF De-coupling capacitor for VDD
C2 100 nF De-coupling capacitor for VDD
C3 1 µF Value can vary depending on codec needs
C4 47 nF Value can vary depending on FM matching network needs. If FM transmission is not being supported by the application this capacitor is not needed
L1 180 nF Value can vary depending on FM matching network needs. If FM transmission is not being supported by the application this inductor is not needed and GNDA must be shorted to GND

10.2.1 Design Requirements

10.2.1.1 Standard I2C Interface Details

The bi-directional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by the master sending a START condition, a high-to-low transition on the SDA line while the SCL line is high. After the start condition, the device address byte is send, MSB first, including the data direction bit (R/W). This device does not respond to the general call address. After receiving the valid address byte (0x77 read, 0x76 write), this device responds with an ACK, a low on the SDA line during the high of the ACK-related clock pulse.

The data byte follows the address ACK. The R/W bit is kept low for transfer from the master to the slave. The data byte is followed by an ACK sent from this device. Data are output only if complete bytes are received and acknowledged. The output data is valid at time (tpv) after the low-to-high transition of SCL, during the clock cycle for the ACK.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (START or STOP).

A Stop condition, a low-to-high transition on the SDA line while the SCL line is high, is sent by the master. The number of data bytes transferred between the start and the stop conditions from the transmitter to receiver is not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit.

A slave receiver that is addressed must generate an ACK after the reception of each byte. The device that acknowledges has to pull down the SDA line during the ACK clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period. Setup and fold times must be taken into account.

acknwldgmnt_on_i2c_bus_scds358.gifFigure 20. Acknowledgment on the I2C Bus

10.2.1.2 Write Operations

Data is transmitted to the TS3A227E by send the device salve address and setting the LSB to a logic 0. The command byte is sent after the address and determines which register receives the data that follows the command byte. The next byte is written to the specified register on the rising edge of the ACK clock pulse. See Figure 2 and Figure 3 for different modes of write operations.

repeatd_data_wrte_sngl_reg_scds358.gifFigure 21. Repeated Data Write to a Single Register
burst_data_wrte_mltpl_reg_scds358.pngFigure 22. Burst Data Write to Multiple Registers

10.2.1.3 Read Operations

The bus master must send the TS3A227E slave address with the LSB set to logic 0. The command byte is sent after the address and determines which register is accessed. After a restart, the device slave address is sent again but this time the LSB is set to logic 1. Data from the register defined by the command byte then is sent back to the host by the TS3A227E. Data is clicked into the SDA output shift register on the rising edge of the ACK clock pulse. Figure 23 and Figure 24 show read operations that use a restart between the sub-address write and the read operation. A Stop and start condition between the sub-address write and the read operation is also acceptable.

Notes:
1. SDA is pulled low on ACK from the slave or master.
2. Register write always a require sub-address write before writing the first data.
3. Repeated data writes to a single register continue indefinitely until n I2C Stop or Re-start.
4. Repeated data reads from a single register continue indefinitely until an I2C NACK is received from the master
5. Burst data writes start at the specified register address, then advance to the next register address, even to the read-only registers and continue until the Stop or Re-start. For the read-only registers, data write appears to occur, although the register contents are not changed by the write operations.
6. Burst data reads start at the specified register address, then advance to the next register address and continues until an I2C NACK is received from the master.
repeatd_data_read_sngl_reg_scds358.gifFigure 23. Repeated Data Read From a Single Register
repeatd_data_read_sngl_reg_scds358.gifFigure 24. Burst Data Read From Multiple Registers

10.2.2 Detailed Design Procedure

10.2.2.1 Accessory Insertion

The TS3A227E monitors the DET_TRIGGER pin to determine when an insertion event occurs. A high to low transition one the DET_TRIGGER pin will start the internal de-bounce timer (default 90 ms). This transition is shown in Figure 19. Once the de-bounce timer has expired, it is determined that an accessory is inserted and the detection algorithm is performed to determine what the accessory is and where the ground line is located.

det_trigger_tran_diag_scds358.gifFigure 25. DET_TRIGGER Transition Diagram

Once a DET_TRIGGER transition has occurred, any I2C register changes will not be serviced until after the de-bounce and detection sequence have completed. If DET_TRIGGER transitions from Low to High before the de-bounce period has expired. The I2C register changes will be serviced before a new de-bounce timer is started from another High to Low transition on the DET_TRIGGER pin. The I2C communication has to complete before the next High to Low transition to take effect.

10.2.2.2 Audio Jack Selection

The audio jack the system uses plays a key role in how the system performs and the experience the end user has with the equipment. In real-world scenarios a user might plug in the headset to the audio jack very slowly. This creates a challenging case for the TS3A227E detection mechanism and detection error can occur if care is not taken when designing the components around the TS3A227E.

The main concern for slow plug-in is the detection process may have already started before the headset is fully inserted into the jack. If the detection is running with the headset out of position, a false impedance measurement may occur. For best performance a jack should be chosen that puts the detection mechanism on the TIP pin at the end of physical jack to ensure that it is fully inserted.

The TS3A227E EVM contains test points for all the jack pins and can be blue wired to prototype audio jacks for testing.

10.2.2.3 Switch Status

Table 18 depicts the switch status for each device configuration. A switch diagram is provided in Figure 26.

Table 18. Switch Status

Device State S1 S2 S3PS S3PR S3GS S3GR RING2
GNDFET		 SLEEVE
GNDFET		 RING2
DFET		 SLEEVE
DFET
Default State (No insertion or VDD = 0 V) High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z On On
Detection running High-Z On High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
3-pole On High-Z High-Z High-Z On On On On On On
3-pole with FM support On High-Z High-Z High-Z High-Z On On High-Z High-Z High-Z
4-pole OMTP High-Z High-Z High-Z On On High-Z High-Z On High-Z On
4-pole OMTP with FM support High-Z High-Z High-Z On On High-Z High-Z On High-Z High-Z
4-pole Standard High-Z High-Z On High-Z High-Z On On High-Z On High-Z
4-pole Standard with FM support High-Z High-Z On High-Z High-Z On On High-Z High-Z High-Z
switch_status_table_diag_scds358.gifFigure 26. Switch Diagram

10.2.2.3.1 Switch Status Diagrams

Closed switches are red in Figure 27 through Figure 31. The diagrams reflect switch states when manual switch control is not enabled.

deflt_swtch_no_acces_ins_scds358.gifFigure 27. Default Switch State With No Accessory Inserted
switch_state_drng_det_scds358.gifFigure 28. Switch State During Detection
switch_state_aftr_det_3_pole_scds358.gifFigure 29. Switch State After Detecting a 3-Pole Headphone
switch_state_aftr_det_4_pole_omtp_scds358.gifFigure 30. Switch State After Detection a 4-pole OMTP Headset
switch_state_aftr_det_4_pole_stndrd_scds358.gifFigure 31. Switch State After Detecting a 4-Pole Standard Headset

10.2.2.4 Key Press Detection

10.2.2.4.1 Key Press Thresholds

The TS3A227E features the ability to adjust the key press thresholds on the fly. The default key press bins are shown below with the default values of the threshold registers optimized to detect these keys. The values for the bins represent the equivalent resistance of the key being pressed with the microphone in parallel. Any equivalent resistance outside these bins is not guaranteed to be detected correctly.

KEY TYPICAL RESISTANCE EQUIVALENT RESISTANCE RANGE
Key 1 50 Ω 0 Ω – 66 Ω
Key 2 135 Ω 126 Ω – 156 Ω
Key 3 240 Ω 228 Ω – 264 Ω
Key 4 470 Ω 360 Ω – 680 Ω

The Threshold 1 register (Address 0Dh) adjusts the detection boundary between Key 1 and Key2. The Threshold 2 register (Address 0Eh) adjusts the detection boundary between Key 2 and Key 3. The Threshold 3 register (Address 0Fh adjusts the detection boundary between Key 3 and Key4.

The thresholds are 7 bit values that can be adjusted for the following formula.

Equation 1. Target bin boundary = KP Threshold[6:0] × 6 Ω

It is important for the proper operation of the KP detection algorithm that the thresholds be ordered correctly: KP Threshold 1< KP Threshold 2 < KP Threshold 3. Placing them out of order will cause incorrect keys to be detected. For information on defining the key press gray zones see the Key Press Gray Zones section.

10.2.2.4.2 System Requirements

The Key Press detection algorithm has the following system requirements to be function properly:

  • MICBIAS output voltage equivalent to key press settings 2 register value within 2.5%
  • MICBIAS pullup resistance equal to 2.2 kΩ ±1%
  • Audio jack contact resistance must be limited to < 100 mΩ. See further information below.

Figure 32 depicts the resistor network without the TS3A227E switches for simplicity.

sys_req_headset_key_netwrk_scds358.gifFigure 32. Headset Microphone and Key Network

When the user presses a key it creates a voltage divider network between the MICBIAS output of the codec and the system ground. This will be a measurable voltage on the SLEEVE/RING2 pin that follows Equation 2. Note that this is simplified because it does not include the TS3A227E switches or the contact resistance of the jack itself.

Equation 2. Eq01_Vsleeve_scds358.gif

The REQ can be calculated with the following:

Equation 3. Eq02_req_scds358.gif

As a result of the above calculations, an ADC attempting to detect the voltage on SLEEVE/RING2 to determine which key is pressed (whichever is the microphone pin) is reliant on the accuracy on the MICBIAS output and the 2.2 kΩ pull-up resistor. The key press bins are targeted assuming ideal values for these system conditions and then the gray zone between the bins takes into account the system variations. As a result the better the accuracy of the MICBIAS output and pull-up resistor the better the accuracy of the key press detection.

In addition to the above, the contact resistance of the audio jack itself can play a role in how accurate the key press detection is. A general rule is less contact resistance is better. In the figure below a more complete picture of the system and the voltage the TS3A227E will detect is shown.

sys_req_vltg_detect_scds358.gif

The red line denotes the current path for the output of the codec to follow when it enters the speakers and eventually sinks into the GNDFETs of the TS3A227E. This audio current adds a voltage offset at the audio jack contact resistance, the trace routing resistance, and the GNDFET itself. Because the TS3A227E has kelvin connections to the jack via the SLEEVE_SENSE RING2_SENSE pins the trace routing resistance and GNDFET induced voltage offsets can be compensated.

However, the jack contact resistance is not visible by the device and cannot be compensated for. To maintain the default bin targets the system must ensure that for a given audio jack contact resistance the max current being output by the codec/amplifier lies below the curve in Figure 34. This ensures a max error introduced of 5 mV into the KP detection algorithm.

10.2.2.4.3 Key Press Grey Zones

When defining custom bins and thresholds it is important to also correctly define the “gray zone” between the bins to ensure that the system will always correctly identify the key that is being pressed. The gray zone region accounts for the absolute error in key press detection, encompasses the error of the internal ADC along with errors from system tolerances and variation. The equation below can be used to determine the gray zone required between each of the bins. Note that the size of the gray zone will vary depending on the actual value of the key press threshold.

Equation 4. Gray Zone = ± [(Ɛ(ADC,GAIN) + ƐMICBIAS + ƐRBIAS + Ɛ(CONT,GAIN) ) × R(KP Threshold) + (Ɛ(ADC,OFF) + Ɛ(CONT,OFF) + KBUFF ) × 6 Ω]
TERM DESCRIPTION VALUE UNIT
Ɛ(ADC,GAIN) Internal ADC gain error 0.015%
ƐMICBIAS Codec MICBIAS output voltage variation. Default bin values assume an output variation of 2.5%. 0.025%(1)
ƐRBIAS MICBIAS resistor variation. Default bin values assume a 1% tolerance of the 2.2 kΩ MICBIAS resistor. 0.01%(1)
ƐCONT.GAIN Gain error introduced by contact resistance of the audio jack. Inline1_rcontact_scds358.gif
ƐKP Threshold KP threshold target identified by system. E.g. the KP Threshold between bins 1 and 2 for the default key press bins is 96 Ω. Defined by system(1) Ω
ƐADC,OFF Internal ADC offset and linearity error 1.5 LSB
ƐCONT,OFF Offset error introduced by contact resistance of the audio jack. Inline2_Rcontact_scds358.gif LSB
KBUFF Buffer constant added to total system gray zone to ensure bin values are detected correctly. It is recommended to use a minimum of 2 for this when defining key gray zones to ensure system level margins. 2 LSB
RContact Max contact resistance of audio jack Defined by system(1) Ω
IMAX Maximum combined (Right and Left) audio output current into the jack. Defined by system(1) A
VMICBIAS MICBIAS output voltage of the codec Defined by system(1) V
(1) These values can vary depending on the system

Example Calculation

The default KP Threshold 1 value for the TS3A227E is 10h or 96 Ω. Using the Gray Zone equation the specified gray zone between keys 1 and 2 can be confirmed assuming the following:

  • VMICBIAS = 2.2 V
  • IMAX × RContact = 5 mV
  • R(KP Threshold) = 96 Ω
  • Default values for all other terms
Equation 5. Eq04_grayzone_scds358.gif

This yields a gray zone of ± 27 Ω. The KP Threshold 1 gray zone can be used to identify the upper limit of key 1 and the lower limit of key 2:

Bin 1 upper limit = KP Threshold 1 – Gray Zone 1
Bin 2 lower limit = KP Threshold 1 + Gray Zone 1

This formula yields an upper limit of 69 Ω. Because each LSB is 6 Ω we round down to the even number of 66 Ω. For the beginning of key 2 we set the value at (96 Ω + 27 Ω) or 126 Ω (123 Ω rounded up to the nearest LSB). This method can be used to define the rest of the key bin thresholds.

10.2.2.4.4 Behavior

The TS3A227E can monitor the microphone line of a 4-pole headset to detect up to 4 key presses/releases and report the key press events back to the host. The key press detection must be activated manually by setting the KP Enable bit of the Device Settings 2 register. To ensure proper operation the MICBIAS voltage must be applied to MICP before enabling key press detection.

behavior_prpr_key_prs_en_seq_scds358.gifFigure 33. Proper Key Press Enable Sequence

The TS3A227E monitors the S3 switch matrix to determine the location of the microphone. If the Manual Switch Control bit is set to ‘1’, the S3 matrix must be configured in one of the following 2 configurations for the key press detection to operate. Other configurations are not supported with key press detection.

S3PR S3PS S3GR S3GS MIC LOCATION
On High-Z High-Z On RING2
High-Z On On High-Z SLEEVE

If the voltage on the microphone line drops below the key press detection threshold for a duration longer than the key press de-bounce time, the key press is considered to be valid. At this point the detected key has the corresponding Key # Press interrupt bit set to ‘1’ and the interrupt is asserted. The corresponding Key # Release interrupt is cleared at the same time the Key # Press interrupt is set.

Once the key is released for a duration longer than the key release de-bounce time, a Key Release interrupt is generated to inform the host that the key has been released. The corresponding Key # released interrupt bit is set to ‘1’ and the interrupt is asserted.

The Key Press interrupt register will clear the contents and return to the default status of 0h when Key Press detection is disabled via an I2C write or a removal event.

Notes about key press detection:

  • The MICBIAS setting adjusts the detection threshold and must be set to the value that is closest to the MICBIAS output of the codec. If the MICBIAS voltage being used is between different MICBIAS settings of the TS3A227E then the closest value that is greater than the MICBIAS voltage should be used.
    • E.G. if the codec output is 2.2 V, the 2.3 V MICBIAS setting in the TS3A227E should be used.
  • If any pending interrupt is not read by the host and a key is pressed, the TS3A227E will continue to run key press detection until the Key Press Enable bit is set to ‘0’

The host will interpret Key Press and Release interrupts using the following pseudo-code:

If (Key # Press && Key # Release) { Key # was pressed one time and is not being held. } else if (Key # Release ) { Key # is being pressed, start the key press duration timer } else if (Key # Release) { Key # has been released, end the key press duration timer }

The key press duration timer the host starts after reading that a key is pressed can be used as follows:

If (Key # Press Duration Timer > XXX ms) { The Key # is being held down, handle accordingly. E.g. if Key # is the volume up key, the system will increment the volume until the Key # Release interrupt is read from the TS3A227E }

10.2.2.4.5 Single Key Press Timing

The diagram below depicts a key press event where the MIC is on the SLEEVE pin. If the MIC is on RING2 the timing diagram will be same.

td_single_key_prss_scds358.gif
A. At this point the SLEEVE voltage has stopped glitching and the Key Press De-bounce timer will no longer restart.
B. Point B is the end of the key press de-bounce period. INT will be asserted with the Key Press bit set.
C. The host read and clears the interrupt register, de-asserting the INT pin.
D. Here the key is released and the key release de-bounce period begins.
E. The key release de-bounce period ends and the INT pin is asserted again with the Key Release bit set.
F. Here the host reads and clears the interrupt register, de-asserting the INT pin.

10.2.2.4.6 Multiple Key Press Timing

The diagram below depicts a multiple key press event in which the host does not immediately read the interrupt register. The MIC is on the SLEEVE pin in this diagram. If the MIC is on RING2 the timing diagram will be the same.

NOTE

If the KP Enable bit is set to ‘0’ during key press detection, key press detection will stop immediately and all the key press/release bits will be cleared.

td_multiple_key_prss_scds358.gif
A. The SLEEVE voltage drops below the Key Press Detection threshold and the Key Press De-bounce timer is started
B. The end of the key press de-bounce timer. Key 1 is detected, the Key 1 Press interrupt is set and the interrupt line is asserted. The Key 1 Release interrupt is cleared.
C. The SLEEVE voltage rises to MICBIAS as the key is released. The Key Release de-bounce timer is started.
D. The Key Release de-bounce timer expires. The Key 1 Release bit is set and the interrupt is asserted.
E. The SLEEVE voltage drops below the Key Press Detection threshold and the Key Press De-bounce timer is started
F. The end of the key press de-bounce timer. Key 2 is detected, the Key 2 Press interrupt is set and the interrupt line is asserted. The Key 2 Release interrupt is cleared.
G. The SLEEVE voltage rises to MICBIAS as the key is released. The Key Release de-bounce timer is started.
H. The Key Release de-bounce timer expires. The Key 2 Release bit is set and the interrupt is asserted.
I. The SLEEVE voltage drops below the Key Press Detection threshold and the Key Press De-bounce timer is started
J. The end of the key press de-bounce timer. Key 1 is detected, the Key 1 Press interrupt is set and the interrupt line is asserted. The Key 1 Release interrupt is cleared.
K. The host reads the I2C interrupt register and sees the following interrupts:
● Key 1 Press
● Key 2 Press
● Key 2 Release
Using the pseudo-code in the key press detection section this is interpreted as:
● Key 2 was pressed one time and is not being held
● Key 1 is currently pressed, start the key press duration timer

10.2.2.4.7 Raw Data Key Press Detection

In addition to threshold adjustment the TS3A227E features the ability to utilize the internal ADC raw output with the Raw Data En bit of the Device Setting 2 register.

Notes on using the Raw ADC Output:

  • Key Press/Release interrupts that have not been serviced will not be cleared upon setting the Raw Data En bit to ‘1’.
  • By Setting the Raw Data En bit to ‘1’ the Key Press Threshold registers will be ignored. Instead of reporting key 1 through 4 press and releases the TS3A227E will only use Key 1 Press to indicate that a key is pressed and the Key 1 Release interrupt to report that the key was released.
  • The ADC Output register will only be cleared after the Raw Data En bit is cleared. The Raw Data En bit is cleared if the Key Press Enable bit is set to ‘0’. Consequently the ADC Output register clears if the Raw Data En bit is set to ‘0’, the Key Press Enable bit is set to ‘0’, or a removal event occurs. This means the ADC Output register will not clear after it is read.
  • A manual software trigger can be initiated after a key was pressed to run the ADC detection again. This will not set the Key 1 Press interrupt.
  • The ADC Output is updated after a Key is detected or if the manual ADC trigger bit is set to ‘1’. If an ADC conversion has completed the ADC Conversion interrupt bit will be set to ‘1’ regardless if there was a software initiated trigger or if a new key press was detected.
  • If the ADC has completed a conversion the output is always non 0 meaning the lowest possible detection threshold of the ADC is 01h. If the ADC Output register is 00h a conversion has not been completed or the ADC Output was cleared.

The previous section on gray zones should be applied to any bins create for the raw ADC mode.

10.2.3 Application Curves

D001_SCDS358.gifFigure 34. Max Current vs Contact Resistance