SCDS387 October   2018 TS3A5017-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics for 3.3-VSupply
    6. 6.6 Electrical Characteristics for 2.5-VSupply
    7. 6.7 Switching Characteristics for 3.3-VSupply
    8. 6.8 Switching Characteristics for 2.5-VSupply
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics for 2.5-VSupply

V+ = 2.3 V to 2.7 V, TA = –40°C to125°C (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Switch
VD, VS Analog signal
range		 0 V+ V
ron ON-state
resistance		 0 ≤ VS ≤ V+,
ID = –24 mA,		 Switch ON,
see Figure 12 		TA = 25°C
V+ = 2.3 V		 22 Ω
TA = Full
V+ = 2.3 V		 28
Δron ON-state
resistance match between channels		 VS = 1.6 V,
ID = –24 mA,		 Switch ON,
see Figure 12 		TA = 25°C
V+ = 2.3 V		 1 Ω
TA = Full
V+ = 2.3 V		 5
ron(flat) ON-state
resistance flatness		 0 ≤ VS ≤ V+,
ID = –24 mA,		 Switch ON,
see Figure 12 		TA = 25°C
V+ = 2.3 V		 18 Ω
TA = Full
V+ = 2.3 V		 24
IS(OFF) S
OFF leakage
current		 VS = 0.5 V, VD = 2.2 V,
or
VS = 2.2 V, VD = 0.5 V,		 Switch OFF,
see Figure 13 		TA = 25°C
V+ = 2.7 V		 0.05 μA
TA = Full
V+ = 2.7 V		 –0.3 0.3
ISPWR(OFF) VS = 0 to 2.7 V,
VD = 2.7 V to 0,		 TA = 25°C
V+ = 0 V		 0.5
TA = Full
V+ = 0 V		 -15 15
ID(OFF) D
OFF leakage
current		 VS = 0.5 V, VD = 2.2 V,
or
VS = 2.2 V, VD = 0.5V,		 Switch OFF,
see Figure 13 		TA = 25°C
V+ = 2.7 V		 0.05 μA
TA = Full
V+ = 2.7 V		 –0.3 0.3
IDPWR(OFF) VD = 0 to 2.7 V,
VS = 2.7 V to 0,		 TA = 25°C
V+ = 0 V		 0.5
TA = Full
V+ = 0 V		 -20 20
IS(ON) S
ON leakage
current		 VS = 0.5 V, VD = Open,
or
VS = 2.2 V, VD = Open,		 Switch ON,
see Figure 14 		TA = 25°C
V+ = 2.7 V		 0.05 μA
TA = Full
V+ = 2.7 V		 –0.3 0.3
ID(ON) D
ON leakage
current		 VD = 0.5 V, VS = Open,
or
VD = 2.2 V, VS = Open,		 Switch ON,
see Figure 14 		TA = 25°C
V+ = 2.7 V		 0.05 μA
TA = Full
V+ = 2.7 V		 –0.3 0.3
Logic Inputs (IN1, IN2, EN)(2)
VIH Input logic high TA = Full 1.7 V+ V
VIL Input logic low TA = Full 0 0.7 V
IIH, IIL Input leakage
current		 VI = V+ or 0 TA = 25°C
V+ = 2.7 V		 0.05 μA
TA = Full
V+ = 2.7 V		 –1 1
QC Charge injection VGEN = 0, RGEN = 0,
CL = 0.1 nF,		 See Figure 21 TA = Full
V+ = 2.5 V		 3 pC
CS(OFF) S
OFF capacitance		 VS = V+ or GND,
Switch OFF,		 See Figure 15 TA = Full
V+ = 2.5 V		 4.5 pF
CD(OFF) D
OFF capacitance		 VD = V+ or GND,
Switch OFF,		 See Figure 15 TA = Full
V+ = 2.5 V		 18.5 pF
CS(ON) S
ON capacitance		 VS = V+ or GND,
Switch ON,		 See Figure 15 TA = Full
V+ = 2.5 V		 26 pF
CD(ON) D
ON capacitance		 VD = V+ or GND,
Switch ON,		 See Figure 15 TA = Full
V+ = 2.5 V		 26 pF
CI Digital input
capacitance		 VI = V+ or GND, See Figure 15 TA = Full
V+ = 2.5 V		 3 pF
BW Bandwidth RL = 50 Ω,
Switch ON,		 See Figure 17 TA = Full
V+ = 2.5 V		 165 MHz
OISO OFF isolation RL = 50 Ω,
f = 1 MHz,		 See Figure 18 TA = Full
V+ = 2.5 V		 –69 dB
OISO OFF isolation RL = 50 Ω,
f = 10 MHz,		 See Figure 18 TA = Full
V+ = 2.5 V		 –49 dB
XTALK Crosstalk RL = 50 Ω,
f = 1 MHz,		 See Figure 19 TA = Full
V+ = 2.5 V		 –69 dB
XTALK(ADJ) Crosstalk adjacent RL = 50 Ω,
f = 1 MHz,		 See Figure 20 TA = Full
V+ = 2.5 V		 –85 dB
THD Total harmonic
distortion		 RL = 600 Ω,
CL = 50 pF,		 f = 20 Hz to 20 kHz,
see Figure 22 		TA = Full
V+ = 2.5 V		 0.3 %
Supply
I+ Positive supply
current		 VI = V+ or GND, Switch ON or OFF TA = Full
V+ = 2.7 V		 2.5 7 μA
TA = Full
V+ = 2.7 V		 10
(1) The algebraic convention, whereby the most negative value is aminimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held atV+ or GND to ensure proper device operation. Refer to the TI applicationreport, Implications of Slow or Floating CMOS Inputs, literaturenumber SCBA004.