SCDS356C November   2014  – March 2019 TS3DDR4000

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Static Electrical Characteristics
    6. 6.6 Dynamic Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Non-Volatile Dual In-line Memory Module (NVDIMM) application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
      2. 9.2.2 Load Isolation Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.4 Device Functional Modes

When EN pin is driven high, the TS3DDR4000 enters into the power-down mode, in which all channels are isolated and the device consumes less than 5 µA of current. When EN pin is driven low, the A port is routed to either B port or C port depending on the configuration of SEL0 and SEL1 signals. The B and C port can also be partially turned on when SEL0 and SEL1 are not both high or both low. Refer to Table 1 for the control logic details.

Table 1. Logic Control Table

CONTROL PINS FUNCTION
EN SEL0 SEL1
H X X Power –down mode. All channels off (isolated)
L L L Port A to port B ON
Port A to port C OFF (isolated)
L L H A [0,1,4,5,8,9] ↔ B [0,1,4,5,8,9]
A [2,3,6,7,10,11] ↔ C [2,3,6,7,10,11]
All other channels OFF (isolated)
L H L A [2,3,6,7,10,11] ↔ B [2,3,6,7,10,11]
A [0,1,4,5,8,9] ↔ C [0,1,4,5,8,9]
All other channels OFF (isolated)
L H H Port A to port B OFF (isolated)
Port A to port C ON