SCDS430A December 2020 – May 2021 TS3DV642-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Design parameter | Example value | |||
---|---|---|---|---|
VCC | 3.0 V to 3.6 V | |||
VCC decoupling capacitor | 0.1 µF | |||
DDC Pull-up resistors on sink side (only for internal display path) | 47 kΩ to 5 V | |||
DDC Pull-up resistors on source side | 2 kΩ to 5 V | |||
HPD pull-down resistor on source side | 100 kΩ to GND | |||
Pull-up / Pull-down resistors for SEL1 / SEL2 pins | 10 kΩ |