SCDS385B January   2018  – July 2018 TS5MP645

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Powered-Off Protection
      2. 8.3.2 1.8 V Logic Compatible Inputs
      3. 8.3.3 Low Power Disable Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Pin Functions
      2. 8.4.2 Low Power Mode
      3. 8.4.3 Switch Enabled Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YFP|36
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
IDD Active Supply Current VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V		 0 30 60 µA
IDD_PD Power-down Supply current VDD = 1.65 V to 5.5 V
OE = VDD
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V		 0 0.1 1 µA
IDD_PD_1.8 Power-down Supply current VDD = 1.65 V to 5.5 V
OE = 1.8 V
SEL = 0 V to 5.5 V
Dn, CLKn = 0 V		 0 0.1 10 µA
DC CHARACTERISTICS
RON_HS On-state resistance VDD = 1.65 V to 5.5 V
OE = 0 V
Dn,CLKn = -8 mA, 0.2V
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8 mA		 2.45 5.5 Ω
RON_LP On-state resistance VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.2V
DAn, DBn, CLKAn, CLKBn = 1.2 V, -8 mA		 2.65 6.5 Ω
RON_flat_HS On-state resistance flatness VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 0.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 0.3 V,-8 mA		 0.1 Ω
RON_flat_LP On-state resistance flatness VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V, -8 mA		 0.9 Ω
ΔRON_HS On-state resistance match between+and - paths VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 0.2 V
DAn, DBn, CLKAn, CLKBn = 0.2 V, -8 mA		 0.1 Ω
ΔRON_LP On-state resistance match between+and - paths VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = -8 mA, 1.2 V
DAn, DBn, CLKAn, CLKBn = 1.2 V, -8 mA		 0.1 Ω
IOFF Switch off leakage current VDD = 0 V, 1.65 V to 5.5 V
OE = 0 V to 5.5 V
SEL= 0 V to 5.5 V
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V		 -0.5 0.5 µA
ION Switch on leakage current VDD = 1.65 V to 5.5 V
OE = 0 V
SEL= 0 V to 5.5 V
Dn, CLKn = 0 V to 1.3 V
DAn, DBn, CLKAn, CLKBn = 0 V to 1.3 V		 -0.5   0.5 µA
DYNAMIC CHARACTERISTICS
tSWITCH Switching time between channels VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL=50 Ω, CL = 5 pF		 1.5 µs
fSEL_MAX Maximum toggling frequency for the SEL line VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL= 50 Ω, CL=1 pF		 100 kHz
tON_OE Device enable time OE to switch on VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL= 50 Ω, CL= 1 pF		 50 300 µs
tON_VDD Device enable time VDD to switch on VDD = 0 V to 1.65 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL= 50 Ω, CL= 1 pF		 50 300 µs
tOFF_OE Device disable time OE to switch off VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL= 50 Ω, CL= 1 pF		 0.5 1 µs
tOFF_VDD Device disable time VDD to switch off VDD = 5 V to 0 V
VDD ramp rate = 250 µs
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1pF		 0.5 1 ms
tMIN_OE Minimum pulse width for OE VDD = 1.65 V to 5.5 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 500 ns
tBBM Break before make time VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = RL = 50 Ω, CL = 1 pF
DAn, DBn, CLKAn, CLKBn:  0.6 V		 50 ns
tSKEW Intrapair skew VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 1 ps
tSKEW Interpair Skew VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.3 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF		 4 ps
tPD Propagation delay with 100 ps rise time VDD = 1.65 V to 5.5 V
OE = 0 V
Dn, CLKn = 0.6 V
DAn, DBn, CLKAn, CLKBn:  RL = 50 Ω, CL = 1 pF
tRISE = 100 ps		 40 ps
OISO Differential off isolation VDD = 1.65 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV + 200 mVPP (differential)
f = 1250 MHz		 -20 dB
XTALK Differential channel to channel crosstalk VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV + 200 mVPP (differential)
f = 1250 MHz		 -40 dB
BW Differential Bandwidth VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV + 200 mVPP (differential)		 1.5 2 GHz
ILOSS Insertion Loss VDD = 1.65 V to 5.5 V
OE = 0 V
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn: RS = 50 Ω, RL = 50 Ω, CL = 1 pF
VI/O = 200 mV + 200 mVPP (differential)
f = 100 kHz		 -0.4 dB
COFF Off capacitance VDD = 1.65 V to 5.5 V
OE = 0 V, VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V , 0.2 V
f = 1250 MHz		 1.5 pF
CON On capacitance VDD = 1.65 V to 5.5 V
OE = VDD
SEL = 0 V, VDD
Dn, CLKn, DAn, DBn, CLKAn, CLKBn = 0 V , 0.2 V
f = 1250 MHz		 1.5 pF
DIGITAL CHARACTERISTICS
VIH Input logic high (SEL, OE) VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF 1.425 5.5 V
VIL Input logic low (SEL, OE) VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF 0 0.5 V
IIH Input high leakage current (SEL, OE) VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF -5 5 µA
IIL Input low leakage current (SEL, OE) VI/O = 0.6 V, RL = 50 Ω,CL = 5 pF -5 5 µA
RPD Internal pull-down resistance on digital input pins VI/O = 0.6 V, RL = 50 Ω, CL = 5 pF 6 MΩ
CSEL, COE Digital Input capacitance (SEL, OE) f = 1 MHz 5 pF