SLLS783C
May 2009 – March 2016
TSB81BA3E
PRODUCTION DATA.
1
Features
2
Description
3
Revision History
4
Description Continued
5
Pin Configuration and Function
6
Electrical Specfications
6.1
Absolute Maximum Ratings
6.2
Thermal Information
6.3
Recommended Operating Conditions
6.4
Electrical Characteristics, Driver
6.5
Electrical Characteristics, Receiver
6.6
Electrical Characteristics, Device
6.7
Switching Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
TTL Input Data
8.3.2
LVDS Output Data
8.4
Device Functional Modes
8.4.1
Input Clock Edge
8.4.2
Low Power Mode
8.4.3
1394b Port Interface Considerations
8.5
Programming
8.5.1
Power-Class
8.6
Register Maps
8.6.1
Internal Register Configuration
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Port Termination for a 1394 Bilingual Port
9.2.2.2
PHY-LINK Interface
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.1.1
Board Stackup
11.1.2
Digital and Analog Partitioning
11.1.3
Image Planes
11.1.4
Parts Placement
11.1.5
Decoupling Capacitors
11.1.6
3W Rule for SCLK
12
Device and Documentation Support
12.1
Device Support
12.2
Related Links
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
13.1
Designing With PowerPAD Devices (PFP Package Only)
Package Options
Mechanical Data (Package|Pins)
ZAJ|168
MPBG703D
PFP|80
MPQF049B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slls783c_oa
7 Parameter Measurement Information
Figure 1. Test Load Diagram
Figure 3. Dx and CTLx Output Delay Relative to xCLK Waveforms
Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms