7.3.3.1 Reference

The TSC2007-Q1 uses an external voltage reference that is applied to the VDD/REF pin. The upper reference voltage range is the same as the supply voltage range, which allows for simple, 1.2-V to 3.6-V, single-supply operation of the chip.

7.3.3.2 Reference Mode

There is a critical item regarding the reference when making measurements while the switch drivers are on. For this discussion, it is useful to consider the basic operation of the TSC2007-Q1 (see Figure 34). The application used in the following example shows the device being used to digitize a resistive touch screen. If the touch screen controller uses a single-ended reference mode, as shown in Figure 21, a measurement of the current Y position of the pointing device is made by connecting the X+ input to the A-D converter, turning on the Y+ and Y– drivers, and digitizing the voltage on X+. For this measurement, the resistance in the X+ lead does not affect the conversion; it does affect the settling time, but the resistance is usually small enough that this timing is not a concern. However, because the resistance between Y+ and Y– is fairly low, the ON-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a 0-V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition, the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error. Therefore, the TSC2007-Q1 does not support single-ended reference mode.

Figure 21. Simplified Diagram of Single-Ended Reference

This situation is resolved, as shown in Figure 22, by using the differential mode; the +REF and –REF inputs are connected directly to Y+ and Y–, respectively. This mode makes the A-D converter ratiometric. The result of the conversion is always a percentage of the external reference, regardless of how it changes in relation to the ON-resistance of the internal switches.

Figure 22. Simplified Diagram of Differential Reference
(Both Y Switches Enabled, X+ is Analog Input)

7.3.3.3 Touch Screen Settling

In some applications, external capacitors may be required across the touch screen to filter noise picked up by the touch screen (noise generated by the LCD panel or back-light circuitry). These capacitors provide a low-pass filter to reduce the noise, but they also cause a settling time requirement when the panel is touched. The settling time typically shows up as a gain error. The problem is that the input or reference has not settled to its final steady-state value before the A-D converter samples the inputs and provides the digital output. Additionally, the reference voltage may continue to change during the measurement cycle.

To resolve these settling-time problems, the TSC2007-Q1 can be commanded to turn on the drivers only without performing a conversion (see Table 4). Time can then be allowed, before the command is issued, to perform a conversion. Generally, the time it takes to communicate the conversion command over the I²C bus is adequate for the touch screen to settle.

7.3.3.4 Variable Resolution

The TSC2007-Q1 provides either 8-bit or 12-bit resolution for the A-D converter. Lower resolution is often practical for measuring slow changing signals such as touch pressure. Performing the conversions at lower resolution reduces the amount of time it takes for the A-D converter to complete its conversion process, which also lowers power consumption.

7.3.3.5 8-Bit Conversion

The TSC2007-Q1 provides an 8-bit conversion mode (M = 1) that can be used when faster throughput is required, and the digital result is not as critical (for example, measuring pressure). By switching to the 8-bit mode, a conversion result can be read by transferring only one data byte. The internal clock runs twice as fast at 4 MHz.

The faster clock shortens each conversion by four bits and reduces data transfer time, which results in fewer clock cycles and provides lower power consumption.

7.3.3.6 Conversion Clock and Conversion Time

The TSC2007-Q1 contains an internal clock, which drives the state machines inside the device that perform the many functions of the part. This clock is divided down to provide a clock that runs the A-D converter. The frequency of this clock is 4-MHz clock for 8-bit mode, and a 2-MHz clock for the 12-bit mode.

7.3.3.7 Data Format

The TSC2007-Q1 output data are in straight binary format as shown in Figure 23. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise.

1. Reference voltage at converter: +REF – (–REF). See Figure 20.

2. Input voltage at converter, after multiplexer: +IN – (–IN). See Figure 20.

Figure 23. Ideal Input Voltages and Output Codes

7.3.3.8 Touch Detect

The PENIRQ pin can be used as an interrupt to the host. R_IRQ is an internal pullup resistor with a programmable value of either 50 kΩ (default) or 90 kΩ. Write command 1011 (setup command) followed by data 0001 sets the pullup to 90 kΩ.

An example for the Y-position measurement is detailed in Figure 24. The PENIRQ output is pulled high by an internal pullup. While in power-down mode with PD0 = 0, the Y– driver is on and connected to GND, and the PENIRQ output is connected to the X+ input. When the panel is touched, the X+ input is pulled to ground through the touch screen, and the PENIRQ output goes low because of the current path through the panel to GND, initiating an interrupt to the processor. During the measurement cycle for X, Y, and Z position, the X+ input is disconnected from the PENIRQ pulldown transistor to eliminate any pullup resistor leakage current from flowing through the touch screen, thus causing no errors.

In addition to the measurement cycles for X, Y, and Z position, commands that activate the X-drivers, Y-drivers, and Y+ and X-drivers without performing a measurement also disconnect the X+ input from the PENIRQ pulldown transistor, and disable the pen-interrupt output function, regardless of the value of the PD0 bit. Under these conditions, the PENIRQ output is forced low. Furthermore, if the last command byte written to the TSC2007-Q1 contains PD0 = 1, the pen-interrupt output function is disabled and cannot detect when the panel is touched. To re-enable the pen-interrupt output function under these circumstances, a command byte must be written to the TSC2007-Q1 with PD0 = 0.

When the bus master sends the address byte with the R/W bit = 0, and the TSC2007-Q1 sends an acknowledge, the pen-interrupt function is disabled. If the command that follows the address byte contains PD0 = 0, then the pen-interrupt function is enabled at the end of a conversion. This action is approximately 100 µs (12-bit mode) or 50 µs (8-bit mode) after the TSC2007-Q1 receives a STOP or START condition, following the receipt of a command byte (see Figure 30 and Figure 29 for further details about when the conversion cycle begins).

In both cases previously listed, TI recommends that whenever the host writes to the TSC2007-Q1, the master processor masks the interrupt associated to PENIRQ. This masking prevents false triggering of interrupts when the PENIRQ line is disabled in the cases previously listed.

Figure 24. Example of a Pen-Touch Induced Interrupt Through the PENIRQ Pin

7.3.3.9 Preprocessing

The TSC2007-Q1 has a combined MAV filter (median value filter and averaging filter).

7.3.3.9.1 MAV Filter

If the acquired signal source is noisy because of the digital switching circuit, it may necessary to evaluate the data without noise. In this case, the median value filter operation helps remove the noise. The array of seven converted results is sorted first. The middle three values are then averaged to produce the output value of the MAV filter.

The MAV filter is applied to all measurements for all analog inputs including the touch screen inputs, temperature measurements TEMP1 and TEMP2, and auxiliary input AUX. To shorten the conversion time, the MAV filter may be bypassed through the setup command; see Table 4 and Table 5.

Figure 25. MAV Filter Operation (Patent Pending)

Table 1. Timing Requirements for Figure 26

7.5.1.1 I²C Fast or Standard Mode (F/S Mode)

In I²C Fast or Standard (F/S) mode, serial data transfer must meet the timing shown in the Specifications section.

In the serial transfer format of F/S mode, the master signals the beginning of a transmission to a slave with a START condition (S), which is a high-to-low transition on the SDA input while SCL is high. When the master has finished communicating with the slave, the master issues a STOP condition (P), which is a low-to-high transition on SDA while SCL is high, as shown in Figure 28. The bus is free for another transmission after a STOP condition has occurred. Figure 28 shows the complete F/S mode transfer on the I²C, 2-wire serial interface. The address byte, control byte, and data byte are transmitted between the START and STOP conditions. The SDA state is only allowed to change while SCL is low, except for the START and STOP conditions. Data are transmitted in 8-bit words. Nine clock cycles are required to transfer the data into or out of the device (8-bit word plus acknowledge bit).

Figure 28. Complete Fast-Mode or Standard-Mode Transfer

7.5.1.2 I²C High-Speed Mode (HS Mode)

The TSC2007-Q1 can operate with high-speed I²C masters. To do so, the pullup resistor on SCL must be changed to an active pullup, as recommended in the I²C specification.

Serial data transfer format in High-Speed (HS) mode meets the Fast or Standard (F/S) mode I²C bus specification. HS mode can only commence after the following conditions (all of which are in F/S mode) exist:

1. START condition (S)
2. 8-bit master code (00001xxx)
3. Not-acknowledge bit (N)

Figure 29 shows this sequence in more detail. HS-mode master codes are reserved 8-bit codes used only for triggering HS mode, and are not to be used for slave addressing or any other purpose. The master code indicates to other devices that an HS-mode transfer is about to begin and the connected devices must meet the HS-mode specification. Because no device is allowed to acknowledge the master code, the master code is followed by a not-acknowledge bit (N).

After the not-acknowledge bit (N) and SCL have been pulled up to a HIGH level, the master switches to HS mode and enables the current-source pullup circuit for SCL (at time t_H shown in Figure 29). Because other devices can delay the serial transfer before t_H by stretching the LOW period of SCL, the master enables the current-source pullup circuit when all devices have released SCL, and SCL has reached a HIGH level, thus speeding up the last part of the rise time of the SCL.

The master then sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address, and receives an acknowledge bit (A) from the selected slave. After a repeated START (Sr) condition and after each acknowledge bit (A) or not-acknowledge bit (N), the master disables its current-source pullup circuit. This disabling enables other devices, such as the TSC2007-Q1, to delay the serial transfer (until the converted data are stored in the TSC internal shift register) by stretching the LOW period of SCL. The master re-enables its current-source pullup circuit again when all devices have released SCL, and SCL reaches a HIGH level, which speeds up the last part of the SCL signal rise time.

Data transfer continues in HS mode after the next repeated START (Sr), and only switches back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, it is possible for the master to link a number of HS-mode transfers, separated by repeated START conditions (Sr).

Figure 29. Complete High-Speed Mode Transfer

7.5.2.1 Address Byte

The TSC2007-Q1 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are factory-preset to comply with the I²C standard for A-D converters and are always set at 10010. The logic state of the address input pins (A1–A0) determines the two LSBs of the device address to activate communication. Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one time.

The A1–A0 address inputs are read whenever an address byte is received, and must be connected to the supply pin (VDD/REF) or the ground pin (GND). The slave address is latched into the TSC2007-Q1 on the falling edge of SCL after the R/W bit has been received by the slave.

The last bit of the address byte (R/W) defines the operation to be performed. When set to a 1, a read operation is selected; when set to a zero, a write operation is selected. Following the START condition, the TSC2007-Q1 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W bit, the slave device outputs an acknowledge signal on the SDA line.

Bit D0: R/W

1: I²C master read from TSC (I²C read addressing).

0: I²C master write to TSC (I²C write addressing).

7.5.2.2 Command Byte

When the TSC2007-Q1 powers up, the power-down bits must be written to ensure that the device is placed into the mode that achieves the lowest power. Therefore, immediately after power up, send a command byte that sets PD1 = PD0 = 0, so that the device is in the lowest power mode, powering down between conversions.

7.5.2.3 Start a Converter Function or Write Cycle

A conversion or write cycle begins when the master issues the address byte containing the slave address of the TSC2007-Q1, with the eighth bit equal to a 0 (R/W = 0), as shown in Table 2. Once the eighth bit has been received, and the address matches the A1–A0 address input pin setting, the TSC2007-Q1 issues an acknowledge.

When the master receives the acknowledge bit from the TSC2007-Q1, the master writes the command byte to the slave (see Table 3). After the command byte is received by the slave, the slave issues another acknowledge bit. The master then ends the write cycle by issuing a repeated START or a STOP condition, as shown in Figure 30.

Figure 30. Complete I²C Serial Write Transmission

If the master sends additional command bytes after the initial byte, but before sending a STOP or repeated START condition, the TSC2007-Q1 does not acknowledge those bytes.

The input multiplexer channel for the A-D converter is selected when bits C3 through C0 are clocked in. If the selected channel is an X, Y, or Z position measurement, the appropriate drivers turn on once the acquisition period begins.

When R/W = 0, the input sample acquisition period starts on the falling edge of SCL when the C0 bit of the command byte has been latched, and ends when a STOP or repeated START condition has been issued. A-D conversion starts immediately after the acquisition period. The multiplexer inputs to the A-D converter are disabled once the conversion period starts. However, if an X, Y, or Z position is being measured, the respective touch screen drivers remain on during the conversion period. A complete write cycle is shown in Figure 30.

7.5.2.4 Read a Conversion or Read Cycle

For best performance, the I²C bus must remain in an idle state while an A-D conversion is taking place. This idling prevents digital clock noise from affecting the bit decisions being made by the TSC2007-Q1. The master must wait for at least 10 µs before attempting to read data from the TSC2007-Q1 to realize this best performance. However, the master does not need to wait for a completed conversion before beginning a read from the slave, if full 12-bit performance is not necessary.

Data access begins with the master issuing a START condition followed by the address byte (see Table 2) with R/W = 1.

When the eighth bit has been received and the address matches, the slave issues an acknowledge. The first byte of serial data then follows (D11–D4, MSB first).

After the first byte has been sent by the slave, it releases the SDA line for the master to issue an acknowledge. The slave responds with the second byte of serial data upon receiving the acknowledge from the master (D3–D0, followed by four 0 bits). The second byte is followed by a NOT acknowledge bit (ACK = 1) from the master to indicate that the last data byte has been received. If the master somehow acknowledges the second data byte, invalid data are returned (FFh). This condition applies to both 12-bit and 8-bit modes. See Figure 31 for a complete I²C read transmission.

Figure 31. Complete I²C Serial Read Transmission

7.5.2.5 Throughput Rate and I²C Bus Traffic

Although the internal A-D converter has a sample rate of up to 200 kSPS, the throughput presented at the bus is much lower. The rate is reduced because preprocessing manages the redundant work of filtering out noise. The throughput is further limited by the I²C bus bandwidth. The effective throughput is approximately 20 kSPS at 8-bit resolution, or 10 kSPS at 12-bit resolution. This preprocessing saves a large portion of the I²C bandwidth for the system to use on other devices.

Each sample and conversion takes 19 CCLK cycles (12-bit), or 16 CCLK cycles (8-bit). For a typical internal 4-MHz OSC clock, the frequency actually ranges from 3.66 MHz to 3.82 MHz. For V_DD = 1.2 V, the frequency reduces to 3.19 MHz, which gives a 3.19 MHz / 16 = 199 kSPS raw A-D converter sample rate.

As an example, use V_DD = 1.2 V and 12-bit mode with the Fast-mode I²C clock (f_SCL = 400 kHz). The equivalent TSC throughput is at least seven times faster than the effective throughput across the bus (4.65 k × 7 = 32.55 kSPS). The supply current to the TSC for this rate and configuration is 128 µA. To achieve an equivalent sample throughput of 8.2 kSPS using the device without preprocessing, the TSC2007-Q1 consumes only (8.2 or 32.55) × 128 µA = 32.24 µA.

Figure 32. Data Acquisition Cycle (Filter Enabled)

Figure 33. Data Acquisition Cycle (Filter Disabled)