SNLS723
august 2022
TSER4905
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
Package Options
Mechanical Data (Package|Pins)
RTD|64
MPQF141C
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snls723_oa
snls723_pm
1
Features
Single or dual port MIPI DSI receiver
Compliant to D-PHY v1.2 and DSI v1.3.1
Packed 16/18/24/30-bit RGB and 16-bit YCbCr
Loosely packed 18-bit RGB and 20-bit 4:2:2
1 clock lane and 1-4 configurable data lanes per D-PHY Port
Up to
2.5
Gbps/lane
with skew calibration
Supports data lane swap and polarity inversion
Supports both burst and non-burst mode
SuperFrame Unpacking Capability
Suitable for
4K
@ 60 Hz video resolution
V
3
Link Enhanced Video
interface
Supports
10.8/6.75/3.375
Gbps per channel; Up to
21.6
Gbps over dual channels
Coax/STP interconnect support
Port Splitting to enable Y-cable interfaces
Ultra-low latency control channel
Two I2C up to 1MHz (up to 3.4 MHz for local bus access)
High speed GPIOs
Compatibility
V
3
Link Video and V
3
Link Enhanced Video product families
V
3
Link Vision product family
Security and diagnostics
Voltage and temperature monitoring
Line Fault Detection
BIST and pattern generation
CRC and error diagnostics
Unique ID for counterfeit protection
ECC on control bits
Advanced link robustness and EMC control
Data scrambling
Spread spectrum clocking generation (SSCG)
Low power operation
1.8-V and 1.1-V dual power supply
Qualifications
ISO 10605 and IEC 61000-4-2 ESD compliant
64 pin QFN Wettable flanks 9 mm x 9 mm
Temperature Range: −20℃ to +85℃