SNLS696C April   2021  – July 2024 TSER953

PRODUCTION DATA  

1.   1
2. 1 Features
3. 2 Applications
4. 3 Description
5. 4 Pin Configuration and Functions
6. 5 Specifications
   1. 5.1 Absolute Maximum Ratings
   2. 5.2 ESD Ratings
   3. 5.3 Recommended Operating Conditions
   4. 5.4 Thermal Information
   5. 5.5 Electrical Characteristics
   6. 5.6 Recommended Timing for the Serial Control Bus
   7. 5.7 Timing Diagrams
   8. 5.8 Typical Characteristics
7. 6 Detailed Description
   1. 6.1 Overview
   2. 6.2 Functional Block Diagram
   3. 6.3 Feature Description
      1. 6.3.1 CSI-2 Receiver
         1. 6.3.1.1 CSI-2 Receiver Operating Modes
         2. 6.3.1.2 CSI-2 Receiver High-Speed Mode
         3. 6.3.1.3 CSI-2 Protocol Layer
         4. 6.3.1.4 CSI-2 Short Packet
         5. 6.3.1.5 CSI-2 Long Packet
         6. 6.3.1.6 CSI-2 Errors and Detection
            1. 6.3.1.6.1 CSI-2 ECC Detection and Correction
            2. 6.3.1.6.2 CSI-2 Check Sum Detection
            3. 6.3.1.6.3 D-PHY Error Detection
            4. 6.3.1.6.4 CSI-2 Receiver Status
      2. 6.3.2 V3Link Forward Channel Transmitter
         1. 6.3.2.1 Frame Format
      3. 6.3.3 V3Link Back Channel Receiver
      4. 6.3.4 Serializer Status and Monitoring
         1. 6.3.4.1 Forward Channel Diagnostics
         2. 6.3.4.2 Back Channel Diagnostics
         3. 6.3.4.3 Voltage and Temperature Sensing
            1. 6.3.4.3.1 Programming Example
         4. 6.3.4.4 Built-In Self Test
      5. 6.3.5 FrameSync Operation
         1. 6.3.5.1 External FrameSync
         2. 6.3.5.2 Internally Generated FrameSync
      6. 6.3.6 GPIO Support
         1. 6.3.6.1 GPIO Status
         2. 6.3.6.2 GPIO Input Control
         3. 6.3.6.3 GPIO Output Control
         4. 6.3.6.4 Forward Channel GPIO
         5. 6.3.6.5 Back Channel GPIO
   4. 6.4 Device Functional Modes
      1. 6.4.1 Clocking Modes
         1. 6.4.1.1 Synchronous Mode
         2. 6.4.1.2 Non-Synchronous Clock Mode
         3. 6.4.1.3 Non-Synchronous Internal Mode
         4. 6.4.1.4 DVP Compatibility Mode
         5. 6.4.1.5 Configuring CLK_OUT
      2. 6.4.2 MODE
   5. 6.5 Programming
      1. 6.5.1 I2C Interface Configuration
         1. 6.5.1.1 CLK_OUT/IDX
            1. 6.5.1.1.1 IDX
      2. 6.5.2 I2C Interface Operation
      3. 6.5.3 I2C Timing
   6. 6.6 Pattern Generation
      1. 6.6.1 Reference Color Bar Pattern
      2. 6.6.2 Fixed Color Patterns
      3. 6.6.3 Packet Generator Programming
         1. 6.6.3.1 Determining Color Bar Size
      4. 6.6.4 Code Example for Pattern Generator
   7. 6.7 Register Maps
      1. 6.7.1 Main Registers
         1. 6.7.1.1  I2C Device ID Register
         2. 6.7.1.2  Reset
         3. 6.7.1.3  General Configuration
         4. 6.7.1.4  Forward Channel Mode Selection
         5. 6.7.1.5  BC_MODE_SELECT
         6. 6.7.1.6  PLL Clock Control
         7. 6.7.1.7  Clock Output Control 0
         8. 6.7.1.8  Clock Output Control 1
         9. 6.7.1.9  Back Channel Watchdog Control
         10. 6.7.1.10 I2C Control 1
         11. 6.7.1.11 I2C Control 2
         12. 6.7.1.12 SCL High Time
         13. 6.7.1.13 SCL Low Time
         14. 6.7.1.14 Local GPIO DATA
         15. 6.7.1.15 GPIO Input Control
         16. 6.7.1.16 DVP_CFG
         17. 6.7.1.17 DVP_DT
         18. 6.7.1.18 Force BIST Error
         19. 6.7.1.19 Remote BIST Control
         20. 6.7.1.20 Sensor Voltage Gain
         21. 6.7.1.21 Sensor Control 0
         22. 6.7.1.22 Sensor Control 1
         23. 6.7.1.23 Voltage Sensor 0 Thresholds
         24. 6.7.1.24 Voltage Sensor 1 Thresholds
         25. 6.7.1.25 Temperature Sensor Thresholds
         26. 6.7.1.26 CSI-2 Alarm Enable
         27. 6.7.1.27 Alarm Sense Enable
         28. 6.7.1.28 Back Channel Alarm Enable
         29. 6.7.1.29 CSI-2 Polarity Select
         30. 6.7.1.30 CSI-2 LP Mode Polarity
         31. 6.7.1.31 CSI-2 High-Speed RX Enable
         32. 6.7.1.32 CSI-2 Low Power Enable
         33. 6.7.1.33 CSI-2 Termination Enable
         34. 6.7.1.34 CSI-2 Packet Header Control
         35. 6.7.1.35 Back Channel Configuration
         36. 6.7.1.36 Datapath Control 1
         37. 6.7.1.37 Remote Partner Capabilities 1
         38. 6.7.1.38 Partner Deserializer ID
         39. 6.7.1.39 Target 0 ID
         40. 6.7.1.40 Target 1 ID
         41. 6.7.1.41 Target 2 ID
         42. 6.7.1.42 Target 3 ID
         43. 6.7.1.43 Target 4 ID
         44. 6.7.1.44 Target 5 ID
         45. 6.7.1.45 Target 6 ID
         46. 6.7.1.46 Target 7 ID
         47. 6.7.1.47 Target 0 Alias
         48. 6.7.1.48 Target 1 Alias
         49. 6.7.1.49 Target 2 Alias
         50. 6.7.1.50 Target 3 Alias
         51. 6.7.1.51 Target 4 Alias
         52. 6.7.1.52 Target 5 Alias
         53. 6.7.1.53 Target 6 Alias
         54. 6.7.1.54 Target 7 Alias
         55. 6.7.1.55 Back Channel Control
         56. 6.7.1.56 Revision ID
         57. 6.7.1.57 Device Status
         58. 6.7.1.58 General Status
         59. 6.7.1.59 GPIO Pin Status
         60. 6.7.1.60 BIST Error Count
         61. 6.7.1.61 CRC Error Count 1
         62. 6.7.1.62 CRC Error Count 2
         63. 6.7.1.63 Sensor Status
         64. 6.7.1.64 Sensor V0
         65. 6.7.1.65 Sensor V1
         66. 6.7.1.66 Sensor T
         67. 6.7.1.67 CSI-2 Error Count
         68. 6.7.1.68 CSI-2 Error Status
         69. 6.7.1.69 CSI-2 Errors Data Lanes 0 and 1
         70. 6.7.1.70 CSI-2 Errors Data Lanes 2 and 3
         71. 6.7.1.71 CSI-2 Errors Clock Lane
         72. 6.7.1.72 CSI-2 Packet Header Data
         73. 6.7.1.73 Packet Header Word Count 0
         74. 6.7.1.74 Packet Header Word Count 1
         75. 6.7.1.75 CSI-2 ECC
         76. 6.7.1.76 IND_ACC_CTL
         77. 6.7.1.77 IND_ACC_ADDR
         78. 6.7.1.78 IND_ACC_DATA
         79. 6.7.1.79 V3LINK_TX_ID0
         80. 6.7.1.80 V3LINK_TX_ID1
         81. 6.7.1.81 V3LINK_TX_ID2
         82. 6.7.1.82 V3LINK_TX_ID3
         83. 6.7.1.83 V3LINK_TX_ID4
         84. 6.7.1.84 V3LINK_TX_ID5
      2. 6.7.2 Indirect Access Registers
         1. 6.7.2.1 PATGEN Registers
         2. 6.7.2.2 V3Link TX Registers
8. 7 Application and Implementation
   1. 7.1 Application Information
      1. 7.1.1 Power-over-Coax
   2. 7.2 Typical Applications
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
         1. 7.2.2.1 CSI-2 Interface
         2. 7.2.2.2 V3Link Input / Output
         3. 7.2.2.3 Internal Regulator Bypassing
         4. 7.2.2.4 Loop Filter Decoupling
      3. 7.2.3 Application Curve
   3. 7.3 Power Supply Recommendations
      1. 7.3.1 Power-Up Sequencing
         1. 7.3.1.1 System Initialization
            1. 7.3.1.1.1 Example Code for Temperature Ramp Initialization
      2. 7.3.2 Power Down (PDB)
   4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
         1. 7.4.1.1 CSI-2 Guidelines
      2. 7.4.2 Layout Examples
9. 8 Device and Documentation Support
   1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
   2. 8.2 Receiving Notification of Documentation Updates
   3. 8.3 Support Resources
   4. 8.4 Trademarks
   5. 8.5 Electrostatic Discharge Caution
   6. 8.6 Glossary
10. 9 Revision History
11. 10Mechanical, Packaging, and Orderable Information