SBOS878D July   2017  – October 2019 TSV911 , TSV912 , TSV914

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Low-Side Motor Control
      2.      Small-Signal Overshoot vs Load Capacitance
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TSV911
    2.     Pin Functions: TSV912
    3.     Pin Functions: TSV914
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TSV911
    5. 7.5 Thermal Information: TSV912
    6. 7.6 Thermal Information: TSV914
    7. 7.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 2.5 V to 5.5 V
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail-to-Rail Input
      2. 8.3.2 Rail-to-Rail Output
      3. 8.3.3 Packages with an Exposed Thermal Pad
      4. 8.3.4 Overload Recovery
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 Input and ESD Protection
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
  • DCK|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.8 Typical Characteristics

at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
TSV911 TSV912 TSV914 C001_SBOS637.png
Figure 1. Offset Voltage Production Distribution
TSV911 TSV912 TSV914 C003_SBOS839.png
Figure 3. Offset Voltage vs Temperature
TSV911 TSV912 TSV914 C004_SBOS878.gif
VS = 2.5 V to 5.5 V
Figure 5. Offset Voltage vs Power Supply
TSV911 TSV912 TSV914 C007_SBOS878.gifFigure 7. Closed-Loop Gain vs Frequency
TSV911 TSV912 TSV914 C009_SBOS839.png
V+ = 2.75 V, V– = –2.75 V
Figure 9. Output Voltage Swing vs Output Current
TSV911 TSV912 TSV914 C012_SBOS839.png
VS = 5.5 V VCM = (V–) – 0.1 V to (V+) + 0.1 V RL= 10 kΩ
TA= –40°C to 125°C
Figure 11. CMRR vs Temperature
TSV911 TSV912 TSV914 C013_SBOS839.png
VS = 2.5 V to 5.5 V
Figure 13. PSRR vs Temperature
TSV911 TSV912 TSV914 C015_SBOS878.gif
Figure 15. Input Voltage Noise Spectral Density vs Frequency
TSV911 TSV912 TSV914 C018_SBOS839.png
VS = 5.5 V VCM = 2.5 V RL = 2 kΩ
G = 1 BW = 80 kHz f = 1 kHz
Figure 17. THD + N vs Amplitude
TSV911 TSV912 TSV914 C020_SBOS878.gif
Figure 19. Quiescent Current vs Supply Voltage
TSV911 TSV912 TSV914 C024_SBOS878.gif
Figure 21. Open-Loop Output Impedance vs Frequency
TSV911 TSV912 TSV914 C026_SBOS839.png
V+ = 2.75 V V– = –2.75 V RL = 10 kΩ
G = –1 V/V VOUT step = 100 mVp-p
Figure 23. Small-Signal Overshoot vs Load Capacitance
TSV911 TSV912 TSV914 C028_SBOS839.png
V+ = 2.75 V, V– = –2.75 V, G = –10 V/V
Figure 25. Overload Recovery
TSV911 TSV912 TSV914 C031_SBOS839.png
V+ = 2.75 V V– = –2.75 V CL = 100 pF
G = 1 V/V
Figure 27. Large-Signal Step Response
TSV911 TSV912 TSV914 C041_SBOS839.png
PRF = –10 dBm
Figure 29. Electromagnetic Interference Rejection Ratio
Referred to Noninverting Input (EMIRR+) vs Frequency
TSV911 TSV912 TSV914 C037_SBOS839.png
VS = 5.5 V
Figure 31. Phase Margin vs Capacitive Load
TSV911 TSV912 TSV914 C032_SBOS839.png
Figure 33. Large Signal Settling Time (Positive)
TSV911 TSV912 TSV914 C002_SBOS839.png
TA = –40°C to 125°C
Figure 2. Offset Voltage Drift Distribution
TSV911 TSV912 TSV914 C005_SBOS839.png
V+ = 2.75 V, V– = –2.75 V
Figure 4. Offset Voltage vs Common-Mode Voltage
TSV911 TSV912 TSV914 C006b_SBOS878.gif
CL = 10 pF
Figure 6. Open-Loop Gain and Phase vs Frequency
TSV911 TSV912 TSV914 C008_SBOS839.pngFigure 8. Input Bias Current vs Temperature
TSV911 TSV912 TSV914 C011_SBOS878.gif
Figure 10. CMRR and PSRR vs Frequency
(Referred to Input)
TSV911 TSV912 TSV914 C016_SBOS839.png
VS = 5.5 V VCM = (V–) –0.1 V to (V+) –1.4 V RL= 10 kΩ
TA= –40°C to 125°C
Figure 12. CMRR vs Temperature
TSV911 TSV912 TSV914 C014_SBOS839.png
VS = 2.5 V to 5.5 V
Figure 14. 0.1-Hz to 10-Hz Input Voltage Noise
TSV911 TSV912 TSV914 C017_SBOS878.gif
VS = 5.5 V VCM = 2.5 V RL = 2 kΩ
G = 1 VOUT = 0.5 VRMS BW = 80 kHz
Figure 16. THD + N vs Frequency
TSV911 TSV912 TSV914 C019_SBOS839.png
VS = 5.5 V VCM = 2.5 V RL = 2 kΩ
G = –1 BW = 80 kHz f = 1 kHz
Figure 18. THD + N vs Amplitude
TSV911 TSV912 TSV914 C021_SBOS839.png
Figure 20. Quiescent Current vs Temperature
TSV911 TSV912 TSV914 C025_SBOS839.png
V+ = 2.75 V V– = –2.75 V G = 1 V/V
RL = 10 kΩ VOUT step = 100 mVp-p
Figure 22. Small-Signal Overshoot vs Load Capacitance
TSV911 TSV912 TSV914 C036_SBOS839.png
V+ = 2.75 V, V– = –2.75 V
Figure 24. No Phase Reversal
TSV911 TSV912 TSV914 C030_SBOS839.png
V+ = 2.75 V, V– = –2.75 V, G = 1 V/V
Figure 26. Small-Signal Step Response
TSV911 TSV912 TSV914 C034_SBOS839.png
Figure 28. Short-Circuit Current vs Temperature
TSV911 TSV912 TSV914 C038_SBOS878.gif
V+ = 2.75 V, V– = –2.75 V
Figure 30. Channel Separation vs Frequency
TSV911 TSV912 TSV914 C023_SBOS839.png
1.
VS = 5.5 V
Figure 32. Open Loop Voltage Gain vs Output Voltage
TSV911 TSV912 TSV914 C033_SBOS839.png
Figure 34. Large Signal Settling Time (Negative)