SBOSA18C may   2020  – june 2023 TSV911A-Q1 , TSV912A-Q1 , TSV914A-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Revision History
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information: TSV911A-Q1
    5. 7.5 Thermal Information: TSV912A-Q1
    6. 7.6 Thermal Information: TSV914A-Q1
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail-to-Rail Input
      2. 8.3.2 Rail-to-Rail Output
      3. 8.3.3 Overload Recovery
    4. 8.4 Device Functional Modes
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Input and ESD Protection
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Typical Characteristics

at TA = 25°C, VS = 5.5 V, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)

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Figure 7-1 Offset Voltage Production Distribution
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Figure 7-3 Offset Voltage vs Temperature
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VS = 2.5 V to 5.5 V
Figure 7-5 Offset Voltage vs Power Supply
GUID-04C06852-29DD-4BC8-81A2-82AF10D0DDDB-low.gifFigure 7-7 Closed-Loop Gain vs Frequency
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V+ = 2.75 V, V– = –2.75 V
Figure 7-9 Output Voltage Swing vs Output Current
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VS = 5.5 VVCM = (V–) – 0.1 V to (V+) + 0.1 VRL= 10 kΩ
TA= –40°C to 125°C
Figure 7-11 CMRR vs Temperature
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VS = 2.5 V to 5.5 V
Figure 7-13 PSRR vs Temperature
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Figure 7-15 Input Voltage Noise Spectral Density vs Frequency
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VS = 5.5 VVCM = 2.5 VRL = 2 kΩ
G = 1BW = 80 kHzf = 1 kHz
Figure 7-17 THD + N vs Amplitude
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Figure 7-19 Quiescent Current vs Supply Voltage
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Figure 7-21 Open-Loop Output Impedance vs Frequency
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V+ = 2.75 VV– = –2.75 VRL = 10 kΩ
G = –1 V/VVOUT step = 100 mVp-p
Figure 7-23 Small-Signal Overshoot vs Load Capacitance
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V+ = 2.75 V, V– = –2.75 V, G = –10 V/V
Figure 7-25 Overload Recovery
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V+ = 2.75 VV– = –2.75 VCL = 100 pF
G = 1 V/V
Figure 7-27 Large-Signal Step Response
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PRF = –10 dBm
Figure 7-29 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency
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VS = 5.5 V
Figure 7-31 Phase Margin vs Capacitive Load
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Figure 7-33 Large Signal Settling Time (Positive)
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TA = –40°C to 125°C
Figure 7-2 Offset Voltage Drift Distribution
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V+ = 2.75 V, V– = –2.75 V
Figure 7-4 Offset Voltage vs Common-Mode Voltage
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CL = 10 pF
Figure 7-6 Open-Loop Gain and Phase vs Frequency
GUID-3FEA516B-17BA-4F50-B3FF-50198F58AF13-low.pngFigure 7-8 Input Bias Current vs Temperature
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Figure 7-10 CMRR and PSRR vs Frequency (Referred to Input)
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VS = 5.5 VVCM = (V–) –0.1 V to (V+) –1.4 VRL= 10 kΩ
TA= –40°C to 125°C
Figure 7-12 CMRR vs Temperature
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VS = 2.5 V to 5.5 V
Figure 7-14 0.1-Hz to 10-Hz Input Voltage Noise
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VS = 5.5 VVCM = 2.5 VRL = 2 kΩ
G = 1VOUT = 0.5 VRMSBW = 80 kHz
Figure 7-16 THD + N vs Frequency
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VS = 5.5 VVCM = 2.5 VRL = 2 kΩ
G = –1BW = 80 kHzf = 1 kHz
Figure 7-18 THD + N vs Amplitude
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Figure 7-20 Quiescent Current vs Temperature
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V+ = 2.75 VV– = –2.75 VG = 1 V/V
RL = 10 kΩVOUT step = 100 mVp-p
Figure 7-22 Small-Signal Overshoot vs Load Capacitance
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V+ = 2.75 V, V– = –2.75 V
Figure 7-24 No Phase Reversal
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V+ = 2.75 V, V– = –2.75 V, G = 1 V/V
Figure 7-26 Small-Signal Step Response
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Figure 7-28 Short-Circuit Current vs Temperature
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V+ = 2.75 V, V– = –2.75 V
Figure 7-30 Channel Separation vs Frequency
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VS = 5.5 V
Figure 7-32 Open Loop Voltage Gain vs Output Voltage
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Figure 7-34 Large Signal Settling Time (Negative)